ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 127

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
V
support the voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same V
input and output pins. Each bank can support one V
example, when V
3.3-V PCI for inputs and outputs.
On-Chip Termination
Arria GX devices provide differential (for the LVDS technology I/O
standard) and series on-chip termination to reduce reflections and
maintain signal integrity. There is no calibration support for these on-chip
termination resistors. On-chip termination simplifies board design by
minimizing the number of external termination resistors required.
Termination can be placed inside the package, eliminating small stubs
that can still lead to reflections.
Arria GX devices provide two types of termination:
■
■
CCIO
Differential termination (R
Series termination (R
level independently. Each bank also has dedicated VREF pins to
CCIO
is 3.3 V, a bank can support LVTTL, LVCMOS, and
S
)
D
)
Arria GX Device Handbook, Volume 1
REF
Arria GX Architecture
voltage level. For
CCIO
2–119
for