cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet

cy8c5588pvi-115es0

Manufacturer Part Number

cy8c5588pvi-115es0

Description

Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY8C5588PVI-115ES0.pdf (102 pages)

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General Description

With its unique array of configurable blocks, PSoC

analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on

every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including

interfaces such as USB, multimaster I

family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM

microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean

primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities

for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware

updates.

Features

■

Cypress Semiconductor Corporation

Document Number: 001-44094 Rev. *J

Notes

1. GPIOs with opamp outputs are not recommended for use with CapSense.

2. This feature on select devices only. See

32-bit ARM Cortex-M3 CPU core

❐

Low voltage, ultra low power

❐

Versatile I/O system

❐

Digital peripherals

❐

DC to 80 MHz operation

Flash program memory, up to 256 KB, 100,000 write cycles,

20-year retention, and multiple security features

Up to 64 KB SRAM memory

2-KB electrically erasable programmable read-only memory

(EEPROM) memory, 1 million cycles, and 20 years retention

24-channel direct memory access (DMA) with multilayer

AMBA high-performance bus (AHB) bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

Wide operating voltage range: 0.5 V to 5.5 V

High-efficiency boost regulator from 0.5 V input to 1.8 V to

5.0 V output

2 mA at 6 MHz

Low power modes including:

• 2-µA sleep mode with real time clock (RTC) and

• 300-nA hibernate mode with RAM retention

28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)

Any GPIO to any digital or analog peripheral routability

LCD direct drive from any GPIO, up to 46×16 segments

CapSense

1.2 V to 5.5 V I/O interface voltages, up to 4 domains

Maskable, independent IRQ on any pin or port

Schmitt-trigger transistor-transistor logic (TTL) inputs

All GPIOs configurable as open drain high/low,

pull-up/pull-down, High-Z, or strong output

Configurable GPIO pin state at power-on reset (POR)

25 mA sink on SIO

20 to 24 programmable logic device (PLD) based universal

digital blocks (UDBs)

Full CAN 2.0b 16 RX, 8 TX buffers

Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator

Four 16-bit configurable timers, counters, and PWM blocks

Library of standard peripherals

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• SPI, UART, and I

• Many others available in catalog

Library of advanced peripherals

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

• Quadrature decoder

low-voltage detect (LVD) interrupt

support from any GPIO

Ordering Information on page 91

[2]

C, and controller area network (CAN). In addition to communication interfaces, the CY8C55

[1]

•

PRELIMINARY

198 Champion Court

Programmable System-on-Chip (PSoC

5 is a true system-level solution providing microcontroller unit (MCU), memory,

for details.

■

Analog peripherals (1.71 V  V

❐

Programming, debug, and trace

❐

Precision, programmable clocking

❐

Temperature and packaging

❐

PSoC

1.024 V ±0.1% internal voltage reference across –40°C to

+85°C (14 ppm/°C)

Configurable delta-sigma ADC with 8- to 20-bit resolution

• Sample rates up to 192 ksps

• Programmable gain stage: ×0.25 to ×16

• 12-bit mode, 192 ksps, 70-dB signal-to-noise ratio (SNR),

• 16-bit mode, 48 ksps, 89-dB SNR, ±2-bit INL, ±1-bit DNL

Two SAR ADCs, each 12-bit at 1 Msps

80-MHz, 24-bit fixed point digital filter block (DFB) to

implement finite impulse response (FIR) and infinite impulse

response (IIR) filters

Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs

Four comparators with 95-ns response time

Four uncommitted opamps with 25-mA drive capability

Four configurable multifunction analog blocks. Example

configurations are programmable gain amplifier (PGA),

transimpedance amplifier (TIA), mixer, and Sample and Hold

CapSense support

JTAG (4 wire), serial wire debug (SWD) (2 wire), single wire

viewer (SWV), and TRACEPORT interfaces

Cortex-M3 flash patch and breakpoint (FPB) block

Cortex-M3 Embedded Trace Macrocell™ (ETM™)

generates an instruction trace stream.

Cortex-M3 data watchpoint and trace (DWT) generates data

trace information

Cortex-M3 Instrumentation Trace Macrocell (ITM) can be

used for printf-style debugging

DWT, ETM, and ITM blocks communicate with off-chip debug

and trace systems via the SWV or TRACEPORT

Bootloader programming supportable through I

UART, USB, and other interfaces

3- to 74-MHz internal oscillator over full temperature and

voltage range

4- to 33-MHz crystal oscillator for crystal PPM accuracy

Internal PLL clock generation up to 80 MHz

32.768-kHz watch crystal oscillator

Low power internal oscillator at 1, 33, and 100 kHz

–40°C to +85°C degrees industrial temperature

48-pin SSOP, 68-pin QFN and 100-pin TQFP package

options.

±1-bit INL/DNL

•

San Jose, CA 95134-1709

5: CY8C55 Family Datasheet

DDA

 5.5 V)

Revised September 2, 2010

[2]

•

Cortex™-M3

C, SPI,

408-943-2600

)

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