cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 43

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

■
■
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C38 family. The
Document Number: 001-44094 Rev. *J
Eight analog local buses (abus) to route signals between the
different analog blocks
Multiplexers and switches for input and output selection of the
analog blocks
Switch Group
Connection
Small ( ~870 Ohms )
Mux Group
Vddio2
Large ( ~200 Ohms)
P15[4]
P15[5]
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
GPIO
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3]
GPIO
P2[4]
Vccd
Vssd
Switch Resistance
*
*
*
*
*
*
*
*
swinp
swinn
ExVrefL1
ExVrefL
i0
i2
dsm0_qtz_vref1 (1.024V)
*
dsm0_vcm_vref2 (0.7V)
dsm0_qtz_vref2 (1.2V)
dsm0_vcm_vref1
dac_vref (0.256V)
Vdda/4
vpwra/2
SAR_vref1 (1.024V)
*
Vdda/2
Vdda
refbuf_vref1 (1.024V)
en_resvpwra
vpwra
Vdda
SAR_vref2 (1.2V)
cmp0_vref
bg_vda_res_en
refbuf_vref2 (1.2V)
(1.024V)
(0.8V)
en_resvda
swinn
cmp_muxvn[1:0]
*
vref_cmp1
opamp0
abuf_vref_int
(0.256V)
Vdda/2
swfol
(1.024V)
vcmsel[1:0]
Vdda
:
*
en_resvda
sc0_bgref
sc1_bgref
(1.024V)
(1.024V)
swinp
*
refsel[1:0]
*
AMUXBUSL
refmux[2:0]
cmp1_vref
vssa
vssa
refmux[2:0]
opamp2
swfol
*
ADC
Figure 8-1. CY8C55 Analog Interconnect
TS
swout
PRELIMINARY
*
0
0
1
1
GLOBALS
ANALOG
2
2
3
Vss ref
3
VBE
4
4
ExVrefL2
5
5
6
6
bg_vda_swabusl0
7
7
ANALOG
swin
*
0123
0123
BUS
*
LPF
ABUSL0
ABUSL1
ABUSL2
ABUSL3
in0
v0
i0
v2
i2
+
vref_vss_ext
Vp (+)
Vn (-)
out0
+
+
-
vcm
-
-
Vin
Vref
out
Vin
Vref
out
refs
*
out
sc0
sc2
Vrefhi_out
ref
in
COMPARATOR
DSM0
qtz_ref
DAC0
DAC2
ExVrefL1
AMUXBUSL
comp2
comp0
CAPSENSE
SAR ADC
refbufl
ExVrefL
SAR0
*
*
AMUXBUSL
AGL[3]
AGL[2]
AGL[1]
AGL[0]
VIDAC
AGL[6]
AGL[7]
AGL[4]
AGL[5]
SC/CT
refs
LPF
DSM
CY8C55 only
104
*
*
5
36
28
90
SAR1
13
ExVrefR
ExVrefL2
refbufr
analog routing architecture is divided into four quadrants as
shown in
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in
Vrefhi_out
*
comp1
comp3
AMUXBUSR
DAC1
DAC3
ABUSR0
ABUSR1
ABUSR2
ABUSR3
44
AGR[3]
AGR[2]
AGR[1]
AGR[0]
(+) Vp
(-) Vn
Vref
Vref
refs
sc1
Vin
Vin
sc3
*
out1
out
ref
out
out
PSoC
in1
in
AMUXBUSR
AGR[6]
AGR[7]
AGR[5]
v1
i1
v3
i3
AGR[4]
+
+
-
-
ANALOG
3210
3210
BUS
Figure
swin
*
Notes:
* Denotes pins on all packages
76543210
76543210
GLOBALS
®
ANALOG
LCD signals are not shown.
*
5: CY8C55 Family Datasheet
8-1. Each quadrant has four analog globals
*
swout
*
AMUXBUSR
*
Vssa
refmux[2:0]
*
opamp3
swfol
sc3_bgref
(1.024V)
sc2_bgref
(1.024V)
abuf_vref_int
refsel[1:0]
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
(1.024V)
en_resvda
*
refbuf_vref2 (1.2V)
refbuf_vref1 (1.024V)
cmp0_vref
Vdda
Vdda/2
(1.024V)
*
swfol
opamp1
*
ExVrefR
i3
i1
*
2-April-2010
Rev #51
swinp
swinn
swinp
swinn
*
*
*
*
*
*
*
*
*
USB IO
USB IO
GPXT
P15[1]
GPXT
P15[0]
P12[7]
P12[6]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
P15[7]
P15[6]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
P3[5]
P3[4]
P3[3]
P3[2]
P3[1]
P3[0]
Vccd
Vssd
Vddd
P5[7]
P5[6]
P5[5]
P5[4]
P1[7]
P1[6]
SIO
SIO
Page 43 of 102
Figure
8-1.
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