cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 55

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

11.2 Device Level Specifications
Specifications are valid for –40 °C  T
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Document Number: 001-44094 Rev. *J
Notes
V
V
V
V
V
V
V
V
I
Parameter
13. The V
14. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
15. If V
16. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
DD
DDA
DDA
DDD
DDD
DDIO
CCA
CCD
BAT
PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets.
[14]
CCD
[13]
DDIO
and V
supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin  V
Analog supply voltage and input to
analog core regulator
Analog supply voltage, analog regulator
bypassed
Digital supply voltage relative to V
Digital supply voltage, digital regulator
bypassed
I/O supply voltage relative to V
Direct analog core voltage input (Analog
regulator bypass)
Direct digital core voltage input (Digital
regulator bypass)
Voltage supplied to boost converter
Active Mode, V
Execute from Flash cache, see
Controller on page 11
Program Memory on page 15
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in low power
mode)
Sleep timer = ON (= ILO ON at 1 kHz)
WDT = OFF
I
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregu-
lated output mode
Comparator = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregu-
lated output mode
2
CCA
C Wake = OFF
are externally regulated, the voltage difference between V
[15]
Description
DD
= 1.71 V–5.5 V
and
A
 85 °C and T
Flash
SSIO
Cache
PRELIMINARY
SSD
[16] 
J
Analog core regulator enabled
Analog core regulator disabled
Digital core regulator enabled
Digital core regulator disabled
Analog core regulator disabled
Digital core regulator disabled
T = –40 °C
T = 25 °C
T = 85 °C
V
V
V
V
 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
DD
DD
DD
DD
= V
= V
= V
= V
DDIO
DDIO
DDIO
DDIO
CCD
and V
= 1.71–1.95 V T = –40 °C
= 4.5–5.5 V
= 2.7–3.6 V
= 2.7–3.6V
Conditions
CCA
PSoC
must be less than 50 mV.
®
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = 25 °C
T = 85 °C
T = 25 °C
5: CY8C55 Family Datasheet
1.71
1.71
1.71
1.71
1.71
Min
1.8
1.8
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
1.8
1.8
1.8
1.8
–
–
–
–
–
2
–
–
–
–
–
2
–
–
–
–
–
V
V
Max
1.89
1.89
1.89
1.89
5.5
5.5
DDA
DDA
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 55 of 102
DDIO
 V
Units
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
DDA
V
V
V
V
V
V
V
V
.
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