z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 309

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z80189

Manufacturer Part Number
z80189
Description
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer
ZiLOG Semiconductor
Datasheet
I/O Registers
INTERNAL I/O REGISTERS
Register
ASCI Control Register A
Channel 0:
ASCI Control Register A
Channel 1:
By programming IOA7 and IOA6 as the I/O control register, internal I/O
register addresses are relocatable within ranges from
the I/O address space.
Table 57.
CNTLA0
CNTLA1
Mnemonics Address
Internal I/O Registers
0
0
0
1
during RESET
during RESET
MOD 2 1 0
R/W
R/W
bit
bit
0 0 0 Start + 7 bit Data + 1 Stop
0 0 1 Start + 7 bit Data + 2 Stop
0 1 0 Start + 7 bit Data + Parity + 1 Stop
0 1 1 Start + 7 bit Data + Parity + 2 Stop
1 0 0 Start + 8 bit Data + 1 Stop
1 0 1 Start + 8 bit Data + 2 Stop
1 1 0 Start + 8 bit Data + Parity + 1 Stop
1 1 1 Start + 8 bit Data + Parity + 2 Stop
MPE
R/W
MPE
R/W
0
0
Multi Processor Enable
Multi Processor Enable
R/W
Family MPU User Manual
RE
0
R/W
RE
0
Receive Enable
Receive Enable
R/W
TE
Remarks
R/W
0
TE
0
Transmit Enable
Transmit Enable
RTS0
R/W
CKA1D
R/W
1
1
Request to Send
0000H
CKA1 Disable
MPBR/
invalid
EFR
R/W
invalid
MPBR/
EFR
R/W
Multi Processor Bit Receive/
Error Flag Reset
UM005003-0703
Multi Processor Bit Receive/
Error Flag Reset
MOD2 MOD1
R/W
MOD2 MOD1
R/W
1
0
to
0
Z8018x
00FFH
R/W
R/W
0
0
MODE Selection
MODE Selection
MOD0
R/W
MOD0
R/W
0
0
in
293

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