z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 324
z80189
Manufacturer Part Number
z80189
Description
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z80189.pdf
(326 pages)
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308
Memory and I/O Wait state insertion
Memory management unit (MMU)
Memory to ASCI
Memory to memory
MMU Register description
Mode
Modem control signals
N
NMI
Non-maskable interrupt
O
On-chip clock generator
Operation modes
UM005003-0703
Z8018x
Family MPU User Manual
HALT
IOSTOP
SLEEP
SYSTEM STOP
and DMA operation timing diagram
Use
Circuit board design rules
External clock interface
Operating frequencies
Control register
CPU timing
IOC
M1 Enable
M1 temporary enable
74
16
31
33
35
15
18
109
105
84
35
138
72
16
168
60
169
170
13
29
115
P
Pin description
Pin package
Programmable reload timer (PRT)
Programming
PRT
R
Refresh
Register
A0 through CTS1
BUSREQ through RFSH
D0 through INT2
RTS0 through TEND1
TEST through XTAL
64-pin DIP
68-pin PLCC
80-pin QFP
Level-sense
Block diagram
Bus release mode timing diagram
Interrupt request generation
Timer control register
Control register
ASCI Control A0
ASCI Control A1
ASCI Control B
ASCI Status 0
ASCI Status 1
87
3
5
109
4
120
123
157
88
131
8
125
128
7
10
161
10
9
164
14
167
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