z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 91

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

76
UM005003-0703
Z8018x
Family MPU User Manual
A0
D0
Note:
MREQ
Figure 36.
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution
restarts at logical address
IORQ
–
INT0
–
A19
WR
Phi
RD
M1
D7
The TRAP interrupt occurs if an invalid instruction is fetched
during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Last MC
INT0 Mode 0 Timing Diagram
MC: Machine Cycle
T1
INT0 acknowledge cycle
0038H
T2
TW
*
. Both IEF1 and IEF2 flags are reset to
RST instruction
TW
*
PC
T3
Ti
*Two Wait States are automatically inserted
Ti
RST instruction execution
T1
PC is pushed onto stack
T2
SP-1
PCH
T3
T1
SP-2
T2
PCL
0
T3
,