mc68hc908ld60 Freescale Semiconductor, Inc, mc68hc908ld60 Datasheet - Page 104

• Manufacturer Part Number: mc68hc908ld60
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
8.6.4 H & V Sync Output Control Register (HVOCR)
Technical Data
104
HVOCR[1:0]
00
01
10
11
Register Settings
MUL[7:4]
3
5
8
9
Address:
The H&V sync output control register controls the PLL reference input
prescaler and the final free-running waveforms for the sync processor
output signals on HOUT, VOUT, DCLK, and DE pins.
(See
DCLKPH[1:0] — DCLK Output Phase Adjustment
HVOCR[1:0] — Free Running Video Mode Select Bits
Reset:
Read:
Write:
These two bits are programmed to adjust the DCLK output phase.
Each increment adds approximately 2 to 3ns delay to the DCLK output.
These two bits together with MUL[7:4] and VRS[7:4] in the PLL
programming register determine the frequencies of the internal
generated free-running signals for output to HOUT, VOUT, DE, and
DCLK pins, when the SOUT bit is set in the sync processor I/O control
register. These two bits determine the prescaler of PLL reference
clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2;
for other values, the prescaler is 3. Reset clears these bits, setting a
default horizontal frequency of 31.25kHz and a vertical frequency of
60Hz, a video mode of 640×480.
VRS[7:4]
Figure 8-6. H&V Sync Output Control Register (HVOCR)
Section 16. Sync
3
3
6
9
$003F
Bit 7
Clock Generator Module (CGM)
Frequency
31.45kHz
37.87kHz
48.37kHz
64.32kHz
= Unimplemented
HOUT
6
Processor.)
Pin Outputs
5
Frequency
59.91Hz
60.31Hz
60.31Hz
60.00Hz
VOUT
DCLKPH1 DCLKPH0
4
0
Frequency
108MHz
24MHz
40MHz
64MHz
DCLK
R
3
0
MC68HC908LD60
= Reserved
Freescale Semiconductor
2
R
SXGA 1280 × 1024
SVGA 800 × 600
XGA 1024 × 768
DE Video Mode
VGA 640 × 480
Video Modes
HVOCR1 HVOCR0
1
0
—
Rev. 1.1
Bit 0
0