mc68hc908ld60 Freescale Semiconductor, Inc, mc68hc908ld60 Datasheet - Page 188

• Manufacturer Part Number: mc68hc908ld60
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Multi-Master IIC Interface (MMIIC)
14.5.4 Multi-Master IIC Status Register (MMSR)
Technical Data
188
Address:
MMRXIF — Multi-Master IIC Receive Interrupt Flag
Reset:
Read: MMRXIF
Write:
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
1 = New data in data receive register (MMDRR)
0 = No data received
Figure 14-5. Multi-Master IIC Status Register (MMSR)
$006D
Bit 7
Multi-Master IIC Interface (MMIIC)
0
0
MMBR2
NOTE:
CPU bus clock is external clock ÷ 4 = 6MHz
0
0
0
0
1
1
1
1
= Unimplemented
MMTXIF MMATCH MMSRW MMRXAK
6
0
0
Table 14-2. Baud Rate Select
MMBR1
0
0
1
1
0
0
1
1
5
0
MMBR0
4
0
0
1
0
1
0
1
0
1
3
1
Baud Rate
MC68HC908LD60
46.875k
23.437k
11.719k
187.5k
93.75k
5.859k
750k
375k
Freescale Semiconductor
2
0
0
MMTXBE MMRXBF
1
1
—
Rev. 1.1
Bit 0
0