mc68hc908ld60 Freescale Semiconductor, Inc, mc68hc908ld60 Datasheet - Page 201

• Manufacturer Part Number: mc68hc908ld60
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

15.6.4 DDC Master Control Register (DMCR)
MC68HC908LD60
Freescale Semiconductor
—
Rev. 1.1
Address:
SCLIEN — SCL Interrupt Enable
DDC1EN — DDC1 Protocol Enable
ALIF — DDC Arbitration Lost Interrupt Flag
Reset:
Read:
Write:
When this bit is set, the SCLIF flag is enabled to generate an interrupt
request to the CPU. When SCLIEN is cleared, SCLIF is prevented
from generating an interrupt request. Reset clears this bit.
This bit is set to enable DDC1 protocol. The DDC1 protocol will use
the Vsync input (from sync processor) as the master clock input to the
DDC module. Vsync rising-edge will continuously clock out the data
to the output circuit. No calling address comparison is performed. The
SRW bit in DDC status register (DSR) will always read as "1". Reset
clears this bit.
This flag is set when software attempt to set MAST but the BB has
been set by detecting the start condition on the lines or when the DDC
is transmitting a "1" to SDA line but detected a "0" from SDA line in
master mode – an arbitration loss. This bit generates an interrupt
request to the CPU if the DIEN bit in DCR is also set. This bit is
cleared by writing "0" to it or by reset.
1 = SCLIF bit set will generate interrupt request to CPU
0 = SCLIF bit set will not generate interrupt request to CPU
1 = DDC1 protocol enabled
0 = DDC1 protocol disabled
1 = Lost arbitration in master mode
0 = No arbitration lost
Figure 15-5. DDC Master Control Register (DMCR)
$0016
ALIF
Bit 7
0
0
DDC12AB Interface
NAKIF
6
0
0
BB
5
0
MAST
4
0
MRW
3
0
BR2
2
0
DDC12AB Interface
BR1
1
0
DDC Registers
Technical Data
Bit 0
BR0
0
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