mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 100

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
7.5 SIM Counter
7.5.1 SIM Counter During Power-On Reset
7.5.2 SIM Counter and Reset States
Advance Information
100
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the V
level for at least nine consecutive CPU cycles (see
Characteristics (V
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four
CGMXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
The SIM counter is used by the power-on reset (POR) module to allow
the oscillator time to stabilize before enabling the internal bus (IBUS)
clocks. The SIM counter also serves as a prescaler for the computer
operating properly (COP) module. The SIM counter overflow supplies
the clock for the COP module. The SIM counter is 13 bits long and is
clocked by the falling edge of CGMXCLK.
The power-on reset (POR) module detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation (CGM) module to drive the
bus clock state machine.
External reset has no effect on the SIM counter. The SIM counter is free-
running after all reset states. For counter control and internal reset
recovery sequences, see
DD
voltage falls to the V
System Integration Module (SIM)
DD
= 5.0 Vdc
7.4.2 Active Resets from Internal
LVRx
voltage and remains at or below that
10%)). The LVI bit in the SIM reset
MC68HC908MR24
Freescale Semiconductor
21.6 DC Electrical
Sources.
—
Rev. 4.1