mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 351

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.4.1 Polled LVI Operation
18.4.2 Forced Reset Operation
18.4.3 False Reset Protection
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
$FE0F
Addr.
Register Name
LVI Status and Control
Register (LVISCR)
See page 352.
In applications that can operate at V
monitor V
LVIPWR bit must be at logic 1 to enable the LVI module, and the LVIRST
bit must be at logic 0 to disable LVI resets. See
Configuration Register
V
In applications that require V
resets allows the LVI module to reset the MCU when V
V
consecutive CPU cycles. In the MOR, the LVIPWR and LVIRST bits
must be at logic 0 to enable the LVI module and to enable LVI resets.
TRPSEL in the LVISCR selects V
The V
supply noise. In order for the LVI module to reset the MCU,V
remain at or below V
must be above V
out of reset. TRPSEL in the LVISCR selects V
LVRX
LVRX
Figure 18-2. LVI I/O Register Summary
DD
.
level and remains at or below that level for nine or more
pin level is digitally filtered to reduce false resets due to power
Reset:
DD
Read: LVIOUT
Write:
by polling the LVIOUT bit. In the configuration register, the
Low-Voltage Inhibit (LVI)
Bit 7
LVRX
R
R
0
LVRX
+ V
= Reserved
R
6
0
0
(CONFIG). TRPSEL in the LVISCR selects
LVHX
for nine or more consecutive CPU cycles. V
DD
TRPSEL
for only one CPU cycle to bring the MCU
5
0
to remain above V
LVRX
DD
levels below V
.
R
4
0
0
R
3
0
0
LVRX
Section 5.
LVRX
Low-Voltage Inhibit (LVI)
+ V
LVRX
R
2
0
0
Advance Information
DD
LVHX
, enabling LVI
, software can
falls to the
.
R
1
0
0
DD
must
Bit 0
R
0
0
DD
351