mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 274

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface Module (SPI)
13.10 Queuing Transmission Data
Advance Information
274
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high.
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA:CPOL = 1:0).
For a slave, the transmit data buffer allows back-to-back transmissions
without the slave precisely timing its writes between transmissions as in
a system with a single data buffer. Also, if no new data is written to the
data buffer, the last value contained in the shift register is the next data
word to be transmitted.
CPHA:CPOL = 1:0
WRITE TO SPDR
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
1
2
3
6 CPU READS SPSCR WITH SPRF BIT SET.
READ SPSCR
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
READ SPDR
Serial Peripheral Interface Module (SPI)
SPSCK
SPRF
SPTE
MOSI
Figure 13-11. SPRF/SPTE CPU Interrupt Timing
1
MSB BIT
BYTE 1
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7 CPU READS SPDR, CLEARING SPRF BIT.
8
9
LSB MSB BIT
5
4
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
Figure 13-11
6
7
MC68HC908MR24
BIT
5
8
BIT
Freescale Semiconductor
4
BIT
3
BIT
2
BIT
1
shows the
LSB MSB BIT
10
9
BYTE 3
11
—
Rev. 4.1
6
12
BIT
5
BIT
4