mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 359

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

19.4.4 Continuous Conversion
19.4.5 Result Justification
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
before the start of the initial ADC cycle. This results in a fractional ADC
cycle and is represented as the “17th” cycle.
In the continuous conversion mode, the ADC data registers ADRH and
ADRL will be filled with new data after each conversion. Data from the
previous conversion will be overwritten whether that data has been read
or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit is set after the first conversion and will stay set for the next
several conversions until the next write of the ADC status and control
register or the next read of the ADC data register.
The conversion result may be formatted in four different ways:
All four of these modes are controlled using MODE0 and MODE1 bits
located in the ADC clock register (ADCR).
Left justification will place the eight most significant bits (MSB) in the
corresponding ADC data register high, ADRH. This may be useful if the
result is to be treated as an 8-bit result where the two least significant
bits (LSB), located in the ADC data register low, ADRL, can be ignored.
However, ADRL must be read after ADRH or else the interlocking will
prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC
data register high, ADRH, and the eight LSBs in ADC data register low,
ADRL. This mode of operation typically is used when a 10-bit unsigned
result is desired.
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Left justified
Right justified
Left Justified sign data mode
8-bit truncation mode
Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
Advance Information
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