mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 60

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

FLASH Memory
4.5 FLASH Charge Pump Frequency Control
Advance Information
60
HVEN — High-Voltage Enable Bit
MARGIN — Margin Read Control Bit
ERASE — Erase Control Bit
PGM — Program Control Bit
The internal charge pump required for program, margin read, and erase
operations is designed to operate most efficiently with a 2-MHz clock.
The charge pump clock is derived from the bus clock.
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program and erase operations cannot be
performed if the bus clock frequency is below 2 MHz.
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can be set only if
either PGM = 1 or ERASE = 1 and the proper sequence for
program/margin read or erase is followed.
This read/write bit configures the memory for margin read operation.
MARGIN cannot be set if the HVEN = 1. MARGIN will automatically
return to unset if asserted when HVEN is set.
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
set at the same time.
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
set at the same time.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1 = Verify operation selected
0 = Verify operation unselected
1 = Erase operation selected
0 = Erase operation unselected
1 = Program operation selected
0 = Program operation unselected
FLASH Memory
MC68HC908MR24
Freescale Semiconductor
Table 4-1
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shows
Rev. 4.1