mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 350

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mc68hc908mr24

Manufacturer Part Number
mc68hc908mr24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Low-Voltage Inhibit (LVI)
18.4 Functional Description
Advance Information
350
FROM LVISCR
V
DETECTOR
TRPSEL
DD
LOW V
DD
V
V
DD
DD
Figure 18-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V
that level for nine or more consecutive CGMXCLK. V
determined by the TRPSEL bit in the LVISCR (see
LVIPWR and LVIRST are in the configuration register (CONFIG). See
Section 5. Configuration Register
Once an LVI reset occurs, the MCU remains in reset until V
above a voltage, V
only one CPU cycle to bring the MCU out of reset. See
Low-Voltage Inhibit (LVI)
the state of the LVIOUT flag in the LVI status register (LVISCR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices. See
Characteristics (V
> LVI
< LVI
Figure 18-1. LVI Module Block Diagram
CPU CLOCK
TRIP
TRIP
= 0
= 1
ANLGTRIP
FROM CONFIG
LVIPWR
shows the structure of the LVI module. The LVI is enabled
DIGITAL FILTER
Low-Voltage Inhibit (LVI)
DD
V
falls below a voltage, V
DD
LVRX
DD
= 5.0 Vdc
+ V
LVIOUT
Reset. The output of the comparator controls
LVHX
. V
DD
FROM CONFIG
10%).
(CONFIG).
LVIRST
must be above V
LVRX
, and remains at or below
21.6 DC Electrical
MC68HC908MR24
Freescale Semiconductor
Figure
LVRX
LVRX
LVI RESET
7.4.2.5
and V
18-2).
DD
+ V
LVHX
rises
LVHX
Rev. 4.1
are
for
DD

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