mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 215

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mc68hc912bd32

Manufacturer Part Number
mc68hc912bd32
Description
16-bit Device Composed Of Standard On-chip Peripherals
Manufacturer
Freescale Semiconductor, Inc
Datasheet
RIVEC
$xx0A
Receive Interrupt
Vector Register
(RIVEC)
Transmit Interrupt
Vector Register
(TIVEC)
45-sibus
TIVEC
$xx0B
H/S-RESET
H/S-RESET
W
R
W
R
NOTE:
NOTE:
NOTE:
BIT 7
BIT 7
0
0
0
0
Figure 47 Transmit Interrupt Source Register (TIVEC)
Figure 46 Receive Interrupt Source Register (RIVEC)
LOCKIE — Locking Error Interrupt Enable
The LOCKIE bit can only be written if the SFTRES bit in the Module
Configuration register is set.
WAKEIE — WAKEUP Interrupt Enable
The read-only Receive Interrupt Vector Register shows the lowest
numbered message buffer that has its interrupt status flag (IFLG) and its
interrupt enable bit (IENA) set. A hard or soft reset will clear the register.
The Receive Interrupt Vector Register contains only valid data if RXIF is
set.
The read-only Transmit Interrupt Vector Register shows the highest
numbered message buffer that has its interrupt status flag (IFLG) and its
interrupt enable bit (IENA) set. A hard or soft reset will clear the register.
The Transmit Interrupt Vector Register contains only valid data if TXIF is
set.
BIT 6
BIT 6
Freescale Semiconductor, Inc.
0
0
0
0
For More Information On This Product,
1 = A locking error will result in a general interrupt and the module
0 = No interrupt will be generated from this event and the module
1 = A requested wake-up will result in a general interrupt.
0 = No interrupt will be generated from this event.
will enter soft reset.
does not enter soft reset.
Go to: www.freescale.com
BIT 5
BIT 5
0
0
0
0
Byteflight™ Module
BIT 4
BIT 4
0
0
0
0
RIVEC3
TIVEC3
BIT 3
BIT 3
0
1
RIVEC2
TIVEC2
BIT 2
BIT 2
1
0
MC68HC912BD32 Rev 1.0
TIVEC1
RIVEC1
Programmer’s Model
BIT 1
BIT 1
Byteflight™ Module
1
0
TIVEC0
RIVEC0
BIT 0
BIT 0
1
0

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