mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 29

• Manufacturer Part Number: mc68hc912bd32
• Description: 16-bit Device Composed Of Standard On-chip Peripherals
• Manufacturer: Freescale Semiconductor, Inc

9-pins
IPIPE1, IPIPE0
MODB, MODA
ADDR[15:8]
DATA[15:8]
ADDR[7:0]
Pin Name
DATA[7:0]
IOC[7:0]
PW[3:0]
AN[7:0]
RESET
LSTRB
TAGLO
EXTAL
BKGD
TAGHI
ECLK
XIRQ
XTAL
DBE
R/W
IRQ
PAI
Rx
Tx
Pin Number
16–12, 9–7
Table 5 MC68HC912BD32 Signal Description Summary
25–18
46–39
58–51
27, 28
27, 28
3–6
16
26
29
32
33
34
35
35
36
37
38
17
17
76
75
For test the clock divider bypass is activated by setting DIVBYP to 1. The
E-clock rate is 1/2 of the frequency applied to EXTAL.
Freescale Semiconductor, Inc.
Pulse Width Modulator channel outputs.
External bus pins share function with general-purpose I/O ports A and B. In
single chip modes, the pins can be used for I/O. In expanded modes, the pins
are used for the external buses.
Pins used for input capture and output compare in the timer and pulse
accumulator subsystem.
Pulse accumulator input
Analog inputs for the analog-to-digital conversion module
Data bus control and, in expanded mode, enables the drive control of external
buses during external reads.
State of mode select pins during reset determine the initial operating mode of
the MCU. After reset, MODB and MODA can be configured as instruction
queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
E Clock is the output connection for the external bus clock. ECLK is used as a
timing reference and for address demultiplexing.
An active low bidirectional control signal,
MCU to a known start-up state, and an output when COP or clock monitor
causes a reset.
Crystal driver and external clock input pins. On reset all the device clocks are
derived from the EXTAL input frequency. XTAL is the crystal output.
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O.
The low strobe function is the exclusive-NOR of A0 and the internal
(The
Pin used in instruction tagging. See
Indicates direction of data on expansion bus. Shares function with
general-purpose I/O. Read/write in expanded modes.
Maskable interrupt request input provides a means of applying asynchronous
interrupt requests to the MCU. Either falling edge-sensitive triggering or
level-sensitive triggering is program selectable (INTCR register).
Provides a means of requesting asynchronous nonmaskable interrupt requests
after reset initialization
Single-wire background interface pin is dedicated to the background debug
function. During reset, this pin determines special or normal operating mode.
Pin used in instruction tagging. See
Byteflight™ receive pin
Byteflight™ transmit pin
For More Information On This Product,
SZ8
Pinout and Signal Descriptions
internal signal indicates the size 16/8 access.)
Go to: www.freescale.com
Description
Development
Development
RESET
acts as an input to initialize the
Pinout and Signal Descriptions
Support.
Support.
MC68HC912BD32 Rev 1.0
Signal Descriptions
SZ8
signal.