mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet
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mpc8309 Summary of contents
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... This document describes the electrical characteristics of MPC8309. To locate published errata or updates for this document, refer to the MPC8309 product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved. ...
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... DDR2 memory controller with 8-bit ECC. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs) ...
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... HDLC Bus (bit rate Mbps) – Asynchronous HDLC (bit rate Mbps) – Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Overview 3 ...
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... Functional and programming compatibility with the MPC8260 interrupt controller — Support for external and internal discrete interrupt sources — Programmable highest priority request — Six groups of interrupts with programmable priority MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0 — Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMCplus, and RS-MMC cards — Card bus clock frequency up to 33.25 MHz. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Overview 5 ...
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... Support for fixed-priority and round-robin channel arbitration – Channel completion reported via optional interrupt requests — Support for scatter/gather DMA processing • IO Sequencer MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... IEEE Std. 1149.1™ compliant JTAG boundary scan 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8309. The MPC8309 is currently targeted to these specifications. Some of these specifications are MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Electrical Characteristics ...
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... OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. 3. Caution: MV must not exceed GV IN power-on reset and power-down sequences. 4. Caution: OV must not exceed OV IN power-on reset and power-down sequences. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 1. Absolute Maximum Ratings Symbol DD1 AV ...
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... Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8309. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage ...
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... PORESET. There is no specific power down sequence requirement for the device. I/O voltage supplies (GV with respect to one another. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 3. Output Drive Capability Output Impedance ( ...
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... V 90% 0 PORESET Figure 3. 3 Power Characteristics The typical power dissipation for this family of MPC8309 devices is shown in Core QUICC Engine Frequency (MHz) Frequency (MHz) 266 200 333 200 400 200 417 233 Notes: 1. The values do not include I/O supply power (OV values, see Table 6 ...
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... QUICC Engine block and other I/Os Note: 1. Typical IO power is based on a nominal voltage of V benchmark application. The measurements were taken on the evaluation board using WC process silicon. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 6. Typical I/O Power Dissipation Parameter 266 MHz, 1 ...
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... SYS_CLK_IN input current SYS_CLK_IN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8309 can be one of two inputs, SYS_CLK_IN or PCI_SYNC_IN, depending on whether the device is configured in PCI host or agent mode. (SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These specifications are also applicable for QE_CLK_IN. ...
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... POR configuration signals consists of CFG_RESET_SOURCE[0:3]. Table 10 provides the PLL lock times. Parameter/Condition PLL lock times 5.1 Reset Signals DC Electrical Characteristics Table 11 provides the DC electrical characteristics for the MPC8309 reset signals mentioned in MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev — KHK SYS_CLK_ IN — ...
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... It is the supply to which far end signal termination is made and is expected equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled Table 13 provides the DDR2 capacitance when GV MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Condition – ...
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... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the equation: t DISKEW value CISKEW MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol DIO = 1.8 V ± ...
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... ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS output setup with respect to MCK MCS output hold with respect to MCK MCK to MDQS Skew MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t MCK D0 D1 ...
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... Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor follows the symbol conventions described in note 1. DDKHMP MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev 1.8V ± 100mV ...
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... MDQS Figure 6 shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x]/ MECC[x] Figure 6. DDR2 SDRAM Output Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor MCK MCK t MCK t (max) = 0.6 ns DDKHMH t (min) = –0.6 ns DDKHMH Figure 5 ...
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... Local Bus 7 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8309. 7.1 Local Bus DC Electrical Characteristics Table 17 provides the DC electrical characteristics for the local bus interface. Table 17. Local Bus DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage = – ...
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... LCLK[n] Input Signals: LAD[0:15] Input Signal: LGTA Output Signals: LBCTL/LBCKE/LOE Output Signals: LAD[0:15] LALE MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor = 50 Figure 7. Local Bus AC Test Load t LBIVKH t LBKHOV ...
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... GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 9. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH t ...
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... The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 DC Electrical Characteristics All MII and RMII drivers and receivers comply with the DC parametric attributes specified in MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t LBKHOZ t LBKHOV ...
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... For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol Conditions OV — ...
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... For example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used MRX with the appropriate letter: R (rise (fall). MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor = 50 Figure 11 ...
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... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). Figure 14 provides the AC test load. Output MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MRX t t ...
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... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t the latter convention is used with the appropriate letter: R (rise (fall). MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t ...
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... Table 25 provides the MII management AC timing specifications. Table 25. MII Management AC Timing Specifications At recommended operating conditions with OV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev RMX t t RMXH RMXF ...
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... R (rise (fall). Figure 17 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 17. MII Management Interface Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor is 3.3 V ± 300mV Symbol Min t 10 ...
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... Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers. 3. The maximum value not only defined by the value of T T1588CLK example, for 10/100 Mbps modes, the maximum value of t MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 27. Symbol ...
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... DC electrical characteristics for the MPC8309 TDM/SI. Table 28. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t T1588CLKOUT t T1588CLKOUTH t T1588OV T1588CLKOUT Figure 18 ...
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... Figure 20 provides the AC test load for the TDM/SI. Output MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol t SEKHOV t SEKHOX ...
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... AC timing specifications for HDLC protocol. Characteristic Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Table 29. Note that although the specifications generally t ...
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... Serial CLK (Input) t HEIVKH Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 23. AC Timing (External Clock) Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol t HEKHOX t HIIVKH t HEIVKH t ...
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... Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications. 11.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8309. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8309 is configured as a host or agent device. ...
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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 25 provides the AC test load for PCI. Output MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol Min t — ...
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... Input current = –100 A High-level output voltage 100 A Low-level output voltage 12.1.2 USB AC Electrical Specifications Table 36 describes the general timing parameters of the USB interface. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t PCIVKH t PCIXKH t PCKHOV t PCKHOX t ...
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... Figure 28 and Figure 29 provide the AC test load and signals for the USB, respectively. Output USBDR_CLK Input Signals t USKHOV Output Signals MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 36. USB General Timing Parameters 1 Symbol t USCK t USIVKH t USIXKH ...
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... DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8309. 13.1 DUART DC Electrical Characteristics Table 37 provides the DC electrical characteristics for the DUART interface of the MPC8309. Table 37. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage –100 A ...
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... MMC Full-speed/High-speed mode SD_CLK clock low time—Full-speed/High-speed mode SD_CLK clock high time—Full-speed/High-speed mode SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev 3 Symbol Condition V — ...
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... VM SD_CK External Clock SD_DAT/CMD Inputs SD_DAT/CMD Outputs Figure 31. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor = 3 Symbol t SHSIXKH t SHSKHOV (first three letters of functional block)(signal)(state) ...
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... FlexCAN AC Timing Specifications Table 42 provides the AC timing specifications for the FlexCAN interface. Table 42. FlexCAN AC Timing Specifications For recommended operating conditions, see Parameter Min Baud rate 10 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 2 Symbol Min — ...
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... Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time 2 Data hold time bus devices Rise time of both SDA and SCL signals MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 2 C interface of the MPC8309. 2 Table 43 Electrical Characteristics of 3.3 V ± ...
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... Figure 32 provides the AC test load for the I Output Figure 33 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Electrical Specifications (continued) Table 43). Symbol t I2CF t I2PVKH t I2KHDX V NL ...
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... Timers This section describes the DC and AC electrical specifications for the timers of the MPC8309. 17.1 Timer DC Electrical Characteristics Table 45 provides the DC electrical characteristics for the MPC8309 timer pins, including TIN, TOUT, TGATE, and RTC_PIT_CLK. Table 45. Timer DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...
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... GPIO 18 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8309. 18.1 GPIO DC Electrical Characteristics Table 11 provides the DC electrical characteristics for the MPC8309 GPIO. Table 47. GPIO DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage ...
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... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. 20 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8309. 20.1 SPI DC Electrical Characteristics Table 51 provides the DC electrical characteristics for the MPC8309 SPI ...
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... Figure 38 represent the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 51. SPI DC Electrical Characteristics Symbol Condition ...
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... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8309. Table 53. JTAG Interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t NEIXKH t NEKHOV t ...
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... JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol Condition V — — ...
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... Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. Figure 39 provides the AC test load for TDO and the boundary-scan outputs of the MPC8309. Output Figure 39. AC Test Load for the JTAG Interface Figure 40 provides the JTAG clock input timing diagram ...
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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 43. Test Access Port Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 42 ...
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... Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8309 is available in a thermally enhanced MAPBGA (mold array process-ball grid array); see Parameters for the MPC8309,” for information on the MAPBGA. 22.1 Package Parameters for the MPC8309 The package parameters are as provided in the following list. ...
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... All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MPC8309 MAPBGA ...
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... MEMC_MDQ14 MEMC_MDQ15 MEMC_MDQ16 MEMC_MDQ17 MEMC_MDQ18 MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 MEMC_MDQ22 MEMC_MDQ23 MEMC_MDQ24 MEMC_MDQ25 MEMC_MDQ26 MEMC_MDQ27 MEMC_MDQ28 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Table 55. MPC8309 Pinout Listing Terminal DDR Memory Controller Interface U5 AA1 ...
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... MEMC_MDQS1 MEMC_MDQS2 MEMC_MDQS3 MEMC_MDQS8 MEMC_MBA0 MEMC_MBA1 MEMC_MBA2 MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev AA4 AA3 IO AC2 IO AB2 IO Y3 ...
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... LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16/ECID_TMODE_IN LA17 LA18 LA19 LA20 LA21 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Local Bus Controller Interface B5 ...
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... LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE_B/LFRE_B LGPL3/LFWP_B LGPL4/LGTA_B/LUPWAIT/LFRB_B LGPL5 LALE UART1_SOUT1 UART1_SIN1 UART1_SOUT2/UART1_RTS_B1/ UART1_SIN2/UART1_CTS_B1/ IIC_SDA1 IIC_SCL1 IIC_SDA2 /CKSTOP_OUT_B/ IIC_SCL2/CKSTOP_IN_B/ IRQ_B0_MCP_IN_B IRQ_B1/MCP_OUT_B/ IRQ_B2/CKSTOP_IN_B/ IRQ_B3/CKSTOP_OUT_B/INTA_B/ SPIMOSI MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev A11 O A10 O C12 O A12 O E13 O D13 O C13 O A13 O B13 O ...
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... SYS_XTAL_OUT PCI_SYNC_IN PCI_SYNC_OUT CFG_CLKIN_DIV_B RTC_PIT_CLOCK QUIESCE_B THERM0 GPIO_0/SD_CLK/MSRCID0 (DDR ID) GPIO_1/SD_CMD/MSRCID1 (DDR ID) GPIO_2/SD_CD/MSRCID2 (DDR ID) GPIO_3/SD_WP/MSRCID3 (DDR ID) GPIO_4/SD_DAT0/MSRCID4 (DDR ID) GPIO_5/SD_DAT1/MDVAL (DDR ID) GPIO_6/SD_DAT2/QE_EXT_REQ_3 GPIO_7/SD_DAT3/QE_EXT_REQ_1 GPIO_8/RXCAN1/LSRCID0/LCS_B4 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor E16 IO E17 IO A19 I D18 JTAG ...
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... USBDR_TXDRXD3/GPIO_35/QE_BRG_2 USBDR_TXDRXD4/GPIO_36/QE_BRG_3 USBDR_TXDRXD5/GPIO_37/QE_BRG_4 USBDR_TXDRXD6/GPIO_38/QE_BRG_9 USBDR_TXDRXD7/GPIO_39/QE_BRG_11 USBDR_PCTL0/UART2_SOUT1/UC2_URM/LB_ POR_CFG_BOOT_ECC USBDR_PCTL1/UART2_SOUT2/UART2_RTS_B 1/LB_POR_BOOT_ERR USBDR_STP/UC3_URM/QE_EXT_REQ_2 PCI_INTA_B PCI_RESET_OUT_B PCI_AD0/BOOT_ROM_ADDR[2] PCI_AD1/BOOT_ROM_ADDR[3] PCI_AD2/BOOT_ROM_ADDR[4] PCI_AD3/BOOT_ROM_ADDR[5] PCI_AD4/BOOT_ROM_ADDR[6] PCI_AD5/BOOT_ROM_ADDR[7] PCI_AD6/CE_PIO_0/BOOT_ROM_ADDR[8] PCI_AD7/BOOT_ROM_ADDR[9] MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev C17 IO E15 IO A18 IO D15 IO C18 IO D16 IO C19 IO USB AA6 I AC9 ...
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... PCI_C_BE_B1 / BOOT_ROM_RDATA[22] PCI_C_BE_B2 / BOOT_ROM_RDATA[23] PCI_C_BE_B3 / /BOOT_ROM_RDATA[24] PCI_PAR/BOOT_ROM_RDATA[25] PCI_FRAME_B / BOOT_ROM_RDATA[26] PCI_TRDY_B / BOOT_ROM_RDATA[27] PCI_IRDY_B / BOOT_ROM_RDATA[28] PCI_STOP_B / BOOT_ROM_RDATA[29] PCI_DEVSEL_B / BOOT_ROM_RDATA[30] PCI_IDSEL / BOOT_ROM_RDATA[31] PCI_SERR_B / BOOT_ROM_MOD_EN PCI_PERR_B / BOOT_ROM_RWB MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor E21 IO H20 IO D22 IO D23 IO J19 IO F21 ...
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... FEC1_RX_ER/GTM1_TGATE2_B/GPIO_20/JTA G_BISE FEC1_RXD0/GPIO_21/JTAG_PRPGPS FEC1_RXD1/GTM1_TIN3/GPIO_22/JTAG_BISR _TDO_EN FEC1_RXD2/GTM1_TGATE3_B/GPIO_23/TPR_ SYS_AAD[0] FEC1_RXD3/GPIO_24/TPR_SYS_AAD[1] FEC1_TX_CLK[CLK10]/GTM1_TIN4/GPIO_25/T PR_SYS_AAD[2] FEC1_TX_EN/GTM1_TGATE4_B/GPIO_26/TPR _SYS_AAD[3] FEC1_TX_ER/GTM1_TOUT4_B/GPIO_27/TPR_ SYS_AAD[4] FEC1_TXD0/GTM1_TOUT1_B/GPIO_28/TPR_S YS_AAD[5] FEC1_TXD1/GTM1_TOUT2_B/GPIO_29/TPR_S YS_AAD[6] FEC1_TXD2/GTM1_TOUT3_B/GPIO_30/TPR_S YS_AAD[7] MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev P21 IO P22 IO T22 IO T21 IO U22 O U21 IO V21 I T19 O U19 O ...
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... FEC2_TX_ER/GTM2_TOUT4_B/GPIO_43/ FEC2_TXD0/GTM2_TOUT1_B/GPIO_44/PD_XL B2MG_DDR_CLOCK FEC2_TXD1/GTM2_TOUT2_B/GPIO_45/ FEC2_TXD2/GTM2_TOUT3_B/GPIO_46/ FEC2_TXD3/GPIO_47/ FEC3_COL/GPIO_48/ FEC3_CRS/GPIO_49/ FEC3_RX_CLK[CLK11]/GPIO_50/ FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO_51/ FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO_52/ FEC3_RXD0/FEC3_TMR_TX_ESFD/GPIO_53/ FEC3_RXD1/FEC3_TMR_RX_ESFD/GPIO_54/ FEC3_RXD2/TSEC_TMR_TRIG1/GPIO_55/ FEC3_RXD3/TSEC_TMR_TRIG2/GPIO_56/ FEC3_TX_CLK[CLK12]/TSEC_TMR_CLK/GPIO _57/ FEC3_TX_EN/TSEC_TMR_GCLK/GPIO_58/ MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor AB17 IO Y15 IO AC17 IO W14 IO AB16 IO Y14 IO AA15 IO AC15 IO AC16 ...
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... HDLC1_CTS_B/GPIO_5/TDM1_RFS/ HDLC1_RTS_B/GPIO_6/TDM1_STROBE_B/CF G_RESET_SOURCE[1] HDLC2_TXCLK[CLK13]/GPIO_16/QE_BRG_7/T DM2_TCK[CLK6] HDLC2_RXCLK[CLK14]/GPIO_17/TDM2_RCK [CLK5]/QE_BRG_8 HDLC2_TXD/GPIO_18/TDM2_TD/CFG_RESET _SOURCE[2] HDLC2_RXD/GPIO_19/TDM2_RD/ HDLC2_CD_B/GPIO_20/TDM2_TFS/ HDLC2_CTS_B/GPIO_21/TDM2_RFS/ HDLC2_RTS_B/GPIO_22/TDM2_STROBE_B/C FG_RESET_SOURCE[3] AVDD1 AVDD2 AVDD3 GVDD MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev AC8 IO AB8 IO AA9 IO AA8 IO AC7 IO HDLC/TDM/GPIO AA20 IO AA21 IO AB22 ...
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... This pin is an open drain signal. A weak pull-up resistor should be placed on this pin This pin has weak pull-up that is always enabled. 4. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor F7, F8, F9, F10, F11, ...
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... PCI Clock Divider CFG_CLKIN_DIV QE PLL QE_CLK_IN The primary clock source for the MPC8309 can be one of three inputs,Crystal(SYS_XTAL_IN ), SYS_CLK_IN or PCI_SYNC_IN, depending on whether the device is configured in PCI host or PCI agent mode, respectively. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Figure 45 ...
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... OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other. 23.2 Clocking in PCI Agent Mode When the MPC8309 is configured as a PCI agent device, PCI_SYNC_IN is the primary input clock. In agent mode, the SYS_CLK_IN signal should be tied to GND, and the clock output signals, PCI_CLKn and PCI_SYNC_OUT, are not used. ...
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... LBC clock divider to create the external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCCR[CLKDIV]. For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8309 PowerQUICC II Pro Communications Processor Reference Manual. ...
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... Section 23, “Clocking,” configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal coherent system bus clock (csb_clk). for selected csb_clk to SYS_CLK_IN ratios. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 1 Max Operating Frequency ...
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... MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 59. CSB Frequency Options 25 csb_clk Frequency (MHz) 2:1 3:1 4:1 5:1 125 6:1 shows the encodings for RCWL[COREPLL]. COREPLL values not listed Table 60. e300 Core PLL Configuration core_clk : csb_clk Ratio ...
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... The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in RCWL[CEVCOD MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor core_clk : csb_clk Ratio 6 0 3:1 0 3:1 0 3:1 NOTE QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ Table 62 ...
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... Suggested PLL Configurations To simplify the PLL configurations, the MPC8309 might be separated into two clock domains. The first domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock domains are independent, and each of their PLLs are configured separately ...
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... Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, T where junction temperature (C) J MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Board type Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) — ...
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... To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( measurement of the temperature at the top center of the package case using the following equation: where junction temperature (C) J MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev ...
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... Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor ...
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... PLL ratio configuration bits as described in • The QUICC Engine PLL (AV Engine block generates or uses external sources for all required serial interface clocks. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev ...
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... Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the MPC8309 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8309 system, and MPC8309 itself requires a clean, tightly regulated source of power ...
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... R measured voltage (1/(1/R 2 – 1). The drive current is then I source term 1 2 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev trimmed until the voltage at the pad equals P )/ Pad Data R P OGND Figure 47 ...
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... Configuration Pin Multiplexing The MPC8309 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking and Initialization” of MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual) ...
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... Parts are marked as in the example shown in Figure 48. Freescale Part Marking for MAPBGA Devices Table 67 shows the SVR Settings. Device MPC8309 MAPBGA Note: PVR = 0x8085_0020 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 66. Part Numbering Nomenclature VM AF e300 Core 2 Package ...
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... Document Revision History Table 68 provides a revision history for this hardware specification. Rev. Date No. 0 03/2011 Initial Release. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Table 68. Document Revision History Substantive Change(s) Document Revision History 81 ...
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... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8309EC Rev. 0 03/2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...