mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 69

• Manufacturer Part Number: mpc8309
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

23.4
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
coherent system bus clock (csb_clk).
for selected csb_clk to SYS_CLK_IN ratios.
Freescale Semiconductor
1
2
3
QUICC Engine frequency (qe_clk)
DDR2 memory bus frequency (MCLK)
Local bus frequency (LCLKn)
The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The DDR2 data rate is 2× the DDR2 memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBCM]).
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
System PLL Configuration
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
Section 23, “Clocking,”
RCWL[SPMF]
Characteristic
0111–1111
Table 57. Operating Frequencies for MAPBGA (continued)
3
0000
0001
0010
0100
0101
0011
0110
Table 58. System PLL Multiplication Factors
2
1
Table 59
the LBCM, DDRCM, and SPMF parameters in the reset
shows the expected frequency values for the CSB frequency
NOTE
System PLL Multiplication Factor
Max Operating Frequency
Table 58
Reserved
Reserved
Reserved
233
167
66
× 2
× 3
× 4
× 5
× 6
shows the multiplication factor
MHz
MHz
MHz
Unit
Clocking
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