mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 72

• Manufacturer Part Number: mpc8309
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Clocking
23.7
To simplify the PLL configurations, the MPC8309 might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs are configured separately.
Table 63
72
Conf No.
10
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
1
2
3
4
5
6
7
8
9
shows suggested PLL configurations for 33 and 66 MHz input clocks.
Suggested PLL Configurations
SPMF
0100
0100
0010
0100
0101
0010
0100
0101
0010
0101
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF)  (1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
0000100
0000101
0000100
0000101
0000101
0000101
0000101
0000110
0000110
0000110
Core
PLL
Table 63. Suggested PLL Configurations
CEPMF
0110
1000
0011
0110
1000
0011
0110
1000
0011
0111
CEDF
0
0
0
0
0
0
0
0
0
0
NOTE
Input Clock
Frequency
(MHz)
33.33
66.67
33.33
66.67
33.33
66.67
33.33
25
25
25
Frequency
133.33
133.33
133.33
133.33
133.33
133.33
166.67
(MHz)
CSB
100
125
125
Frequency
266.66
266.66
333.33
333.33
399.96
399.96
416.67
(MHz)
312.5
Core
250
375
Freescale Semiconductor
Frequency
Engine
QUICC
(MHz)
200
200
200
200
200
200
200
200
200
233