dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 10

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

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PHYAD0 (COL)
PHYAD1 (RXD1_0)
PHYAD2 (RXD0_1)
PHYAD3 (RXD1_2)
PHYAD4 (RXD1_3)
AN_0 (LED_LINK)
MII_MODE (RX_DV)
LED_CFG (CRS/CRS_DV)
MDIX_EN (RX_ER)
7.6 STRAP OPTIONS
The DP83848Q uses many of the functional pins as strap op-
tions. The values of these pins are sampled during reset and
used to strap the device into specific modes of operation. The
strap option pin assignments are defined below. The func-
tional pin name is indicated in parentheses.
Signal Name
S, O, PU
S, O, PD
S, O, PU
S, O, PD
S, O, PU
S, O, PU
Type
Pin #
35
36
37
38
39
22
32
33
34
PHY ADDRESS [4:0]: The DP83848Q provides five PHY address pins, the
state of which are latched into the PHYCTRL register at system Hardware-
Reset.
The DP83848Q supports PHY Address strapping values 0 (<00000>)
through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate
Mode. The Mll isolate mode must be selected by strapping Phy Address 0;
changing to Address 0 by register write will not put the Phy in the Mll isolate
mode. Please refer to section
information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-up resistors.
AN0: This input pin controls the advertised operating mode of the
DP83848Q according to the following table. The value on this pin is set by
connecting the input pin to GND (0) or V
pin should NEVER be connected directly to GND or V
The value set at this input is latched into the DP83848Q at Hardware-Reset.
The float/pull-down status of this pin is latched into the Basic Mode Control
Register and the Auto_Negotiation Advertisement Register during
Hardware-Reset.
The default is 1 since the this pin has an internal pull-up.
MII MODE SELECT: This strapping option determines the operating mode
of the MAC Data Interface. Default operation (No pull-ups) will enable normal
MII Mode of operation. Strapping MII_MODE high will cause the device to
be in the RMII mode of operation. Since the pin includes an internal pull-
down, the default value is 0.
The following table details the configurations:
LED CONFIGURATION: This strapping option determines the mode of
operation of the LED pin. Default is Mode 1. Mode 1 and Mode 2 can be
controlled via the strap option. All modes are configurable via register
access.
See
MDIX ENABLE: Default is to enable MDIX. This strapping option disables
Auto-MDIX. An external pull-down will disable Auto-MDIX mode.
MII_MODE
Table 3
AN0
10
0
1
0
1
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is re-
quired, then there is no need for external pull-up or pull down
resistors. Since these pins may have alternate functions after
reset is deasserted, they should not be connected directly to
V
for LED Mode Selection.
CC
or GND.
10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
Section 8.3 PHY ADDRESS
Description
MAC Interface Mode
Advertised Mode
CC
RMII Mode
(1) through 2.2 kΩ resistors. This
MII Mode
CC
for additional
.