dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 22

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

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10.1.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and scram-
bled, the data must be NRZI encoded in order to comply with
the TP-PMD standard for 100BASE-TX transmission over
Category-5 Unshielded twisted pair cable.
10.1.4 Binary to MLT-3 Convertor
The Binary to MLT-3 conversion is accomplished by convert-
ing the serial binary data stream output from the NRZI en-
coder into two binary data streams with alternately phased
logic one events. These two binary streams are then fed to
the twisted pair output driver which converts the voltage to
current and alternately drives either side of the transmit trans-
former primary winding, resulting in a MLT-3 signal.
The 100BASE-TX MLT-3 signal sourced by the PMD Output
Pair common driver is slew rate controlled. This should be
considered when selecting AC coupling magnetics to ensure
TP-PMD Standard compliant transition times (3 ns < Tr < 5
ns).
The 100BASE-TX transmit TP-PMD function within the
DP83848Q is capable of sourcing only MLT-3 encoded data.
Binary output from the PMD Output Pair is not possible in 100
Mb/s mode.
10.2 100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is provided
to the MII. Because the 100BASE-TX TP-PMD is integrated,
the differential input pins, RD±, can be directly routed from
the AC coupling magnetics.
22
See
function. This provides an overview of each functional block
within the 100BASE-TX receive section.
The Receive section consists of the following functional
blocks:
— Analog Front End
— Digital Signal Processor
— Signal Detect
— MLT-3 to Binary Decoder
— NRZI to NRZ Decoder
— Serial to Parallel
— Descrambler
— Code Group Alignment
— 4B/5B Decoder
— Link Integrity Monitor
— Bad SSD Detection
10.2.1 Analog Front End
In addition to the Digital Equalization and Gain Control, the
DP83848Q includes Analog Equalization and Gain Control in
the Analog Front End. The Analog Equalization reduces the
amount of Digital Equalization required in the DSP.
10.2.2 Digital Signal Processor
The Digital Signal Processor includes Adaptive Equalization
with Gain Control and Base Line Wander Compensation.
Figure 6
for a block diagram of the 100BASE-TX receive