dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 18

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

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9.3 802.3u MII SERIAL MANAGEMENT INTERFACE
9.3.1 Serial Management Register Access
The serial management MII specification defines a set of thir-
ty-two 16-bit status and control registers that are accessible
through the management interface pins MDC and MDIO. The
DP83848Q implements all the required MII registers as well
as several optional registers. These registers are fully de-
scribed in
serial management access protocol follows.
9.3.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management
Data Clock (MDC) and Management Data Input/Output
(MDIO). MDC has a maximum clock rate of 25 MHz and no
minimum rate. The MDIO line is bi-directional and may be
shared by up to 32 devices. The MDIO frame format is shown
below in
The MDIO pin requires a pull-up resistor (1.5 kΩ) which, dur-
ing IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848Q with a sequence that can be used to
establish synchronization. This preamble may be generated
either by driving MDIO high for 32 consecutive MDC clock
cycles, or by simply allowing the MDIO pull-up resistor to pull
the MDIO pin high during which time 32 MDC clock cycles are
Read Operation
Write Operation
Start Threshold RBR[1:0]
MII Management Serial Protocol
Table
Section 13.0 Register
3 (12-bits)
0 (16-bits)
1 (4-bits)
2 (8-bits)
5.
TABLE 4. Supported Packet Sizes at +/-50ppm +/-100ppm For Each Clock
Block. A description of the
Latency Tolerance
FIGURE 3. Typical MDC/MDIO Read Operation
10 bits
14 bits
2 bits
6 bits
TABLE 5. Typical MDIO Frame Format
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Recommended Packet Size
18
at +/- 50ppm
12,000 bytes
16,800 bytes
provided. In addition 32 MDC clock cycles should be used to
re-sync the device if an invalid start, opcode, or turnaround
bit is detected.
The DP83848Q waits until it has received this preamble se-
quence before responding to any other transaction. Once the
DP83848Q serial management port has been initialized no
further preamble sequencing is required until after a power-
on/reset, invalid Start, invalid Opcode, or invalid turnaround
bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between the
Register Address field and the Data field. To avoid contention
during a read transaction, no device shall actively drive the
MDIO signal during the first bit of Turnaround. The addressed
DP83848Q drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data.
shows the timing relationship between MDC and the MDIO as
driven/received by the Station (STA) and the DP83848Q
(PHY) for a typical register read access.
For write transactions, the station management entity writes
data to the addressed DP83848Q thus eliminating the re-
quirement for MDIO Turnaround. The Turnaround time is
filled by the management entity by inserting <10>.
shows the timing relationship for a typical MII register write
access.
2,400 bytes
7,200 bytes
Recommended Packet Size
at +/- 100ppm
1,200 bytes
3,600 bytes
6,000 bytes
8,400 bytes
30152504
Figure 3
Figure 4