adau1381 Analog Devices, Inc., adau1381 Datasheet

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adau1381

Manufacturer Part Number
adau1381
Description
Low-noise Stereo Codec With Enhanced Recording And Playback Processing
Manufacturer
Analog Devices, Inc.
Datasheet

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FEATURES
24-bit stereo audio ADC and DAC
400 mW speaker amplifier (into 8 Ω load)
Built-in sound engine for audio processing
Sampling rates from 8 kHz to 96 kHz
Stereo pseudo differential microphone input
Optional stereo digital microphone input pulse-density
Stereo line output
PLL supporting a range of input clock rates
Analog and digital I/O 1.8 V to 3.3 V
Software control via SigmaStudio graphical user interface
Software-controllable, clickless mute
Software register and hardware pin standby mode
32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP
APPLICATIONS
Digital still cameras
Digital video cameras
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Wind noise detection and autofiltering
Enhanced stereo capture (ESC)
Dual-band automatic level control (ALC)
6-band equalizer, including notch filter
modulation (PDM)
RMIC/RMICN/
LMIC/LMICN/
MICBIAS
RMICP
MICD1
LMICP
MICD2
BEEP
PDN
MICROPHONE
BIAS
PGA
PGA
PGA
FUNCTIONAL BLOCK DIAGRAM
Low Noise Stereo Codec with Enhanced
RIGHT
PLL
LEFT
ADC
ADC
Recording and Playback Processing
REGULATOR
INPUT/OUTPUT PORTS
AUTOMATIC LEVEL
SOUND ENGINE
DIGITAL VOLUME
Figure 1.
NOTCH FILTER
SERIAL DATA
DECIMATION
WIND NOISE
EQUALIZER
CONTROL
CONTROL
FILTERS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADAU1381 is a low power, 24-bit stereo audio codec. The
low noise DAC and ADC support sample rates from 8 kHz to
96 kHz. Low current draw and power saving modes make the
ADAU1381 ideal for battery-powered audio applications.
A configurable sound engine provides enhanced record and
playback processing to improve overall audio quality.
The record path includes two digital stereo microphone inputs
and an analog stereo input path. The analog inputs can be
configured for either a pseudo differential or a single-ended
stereo source. A dedicated analog beep input signal can be
mixed into any output path. The ADAU1381 includes a stereo
line output and speaker driver, which makes the device capable of
supporting dynamic speakers.
The serial control bus supports the I
the serial audio bus is programmable for I
justified, or TDM mode. A programmable PLL supports flexible
clock generation for all standard rates and available master clocks
from 11 MHz to 20 MHz.
RIGHT
LEFT
DAC
DAC
CONTROL PORT
ADAU1381
I
2
C/SPI
©2009–2010 Analog Devices, Inc. All rights reserved.
OUTPUT
MIXER
AOUTL
AOUTR
SPP
SPN
2
C® or SPI protocols, and
ADAU1381
2
S, left-justified, right-
www.analog.com

Related parts for adau1381

adau1381 Summary of contents

Page 1

... Low Noise Stereo Codec with Enhanced Recording and Playback Processing GENERAL DESCRIPTION The ADAU1381 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1381 ideal for battery-powered audio applications ...

Page 2

... ADAU1381 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Record Side Performance Specifications ................................... 4 Output Side Performance Specifications ................................... 6 Power Supply Specifications........................................................ 8 Typical Power Management Measurements ............................. 9 Digital Filters ................................................................................. 9 Digital Input/Output Specifications......................................... 10 Digital Timing Specifications ................................................... 11 Absolute Maximum Ratings .......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution ...

Page 3

... Added Endnote 1 to Table 3 ............................................................. 8 Changes to Figure 23 ...................................................................... 20 Changes to Figure 24 ...................................................................... 21 Changes to Figure 25 ...................................................................... 22 Changes to Figure 26 ...................................................................... 23 Changes to Table 27 ........................................................................ 43 Added Register 16434 (0x4032), Dejitter Control Section ........ 76 Changes to Ordering Guide ........................................................... 84 10/09—Revision 0: Initial Version   Outline Dimensions ........................................................................ 84   Ordering Guide ........................................................................... 84 Rev Page ADAU1381     ...

Page 4

... ADAU1381 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.288 MHz ( kHz, 256 × word width = 24 bits; load capacitance (digital output pF; load current (digital output mA; high level input voltage = 0.7 × IOVDD; ...

Page 5

... AVDD = 3.3 V, 100 mV rms, 1 kHz AVDD = 3.3 V, 100 mV rms, 20 kHz Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −3 dBFS input, measured at AOUTL pin, beep gain set AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. A| Page ADAU1381 Min Typ Max 0 32 −98 50 0.25 −1 −98 −55 −55 AVDD/3.3 ...

Page 6

... ADAU1381 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × ...

Page 7

... AVDD = 3 capacitor = 10 μF AVDD = 3.3 V,100 mV p-p at 217 Hz AVDD = 3.3 V, 100 mV p kHz AVDD = 3.3 V Mute set by Register 0x401F, Bit output power O Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V Rev. A| Page ADAU1381 Min Typ Max 99 94 103 97 92 100 −88 −88 99 103 ...

Page 8

... ADAU1381 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path Muted REFERENCE (CM PIN) Common-Mode Reference Output POWER SUPPLY SPECIFICATIONS AVDD1 and AVDD2 must always be equal ...

Page 9

... Rev. A| Page kHz, analog and digital input tones are S Typical ADC Typical Line Output THD + N (dB) THD + N (dB) 88.5 93.0 88.5 93.0 88.5 93.0 88.5 93.0 88.0 87.5 88.0 87.5 88.0 87.5 88.0 87.5 88.5 94.5 88.5 94.5 88.5 94.5 88.5 94.5 89.0 90.5 89.0 90.5 89.0 90.5 89.0 90.5 88.5 89.5 88.5 89.5 88.5 89.5 88.5 89.5 86.5 85.5 86.5 85.5 86.5 85.5 86.5 85.5 88.5 90.5 88.5 90.5 88.5 90.5 88.5 90.5 88.0 88.0 88.0 88.0 88.0 88.0 88.0 88.0 Factor Min Typ 0.4375 × ±0.015 0.5 × 0.5625 × 22.9844/f 479 S ADAU1381 Max Unit kHz dB kHz kHz dB μs ...

Page 10

... ADAU1381 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −25°C < T < +85°C, IOVDD = 1. 3.63 V, unless otherwise specified. A Table 6. Parameter HIGH LEVEL INPUT VOLTAGE ( LOW LEVEL INPUT VOLTAGE (V ...

Page 11

... Bus-free time. Time between stop and start MΩ Digital microphone clock fall time Digital microphone clock rise time Digital microphone delay time for valid data Digital microphone delay time for data three-stated. Rev. A| Page ADAU1381 = 14 pF. L ...

Page 12

... ADAU1381 Digital Timing Diagrams t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) t BIH BCLK t BIL LRCLK ...

Page 13

... Figure 4. SPI Port Timing SDR SDF t SCR SCLH SCS SCLL SCF 2 Figure Port Timing t t DCF t t DDH DDH t DDV DATA2 DATA1 Figure 6. Digital Microphone Timing Rev. A| Page ADAU1381 t CLH t CLPH t COD t SCH t BFT DCR t DDV DATA2 ...

Page 14

... ADAU1381 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...

Page 15

... MCKO SCL/CCLK 8 17 MCKI NOTES CONNECT. 2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1381 GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 7. 32-Lead LFCSP Pin Configuration ...

Page 16

... Pseudo Differential Source/Digital Microphone Input 1. A_IN Beep Signal Input. PWR Microphone Bias. Exposed Pad. The exposed pad is connected internally to the ADAU1381 grounds. For increased reliability of the solder joints and maximum thermal capability recommended that the pad be soldered to the ground plane. Rev Page ...

Page 17

... S Figure Rev. A| Page 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 f FREQUENCY (NORMALIZED Normalized 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 f FREQUENCY (NORMALIZED Figure 13. ADC Decimation Filter, Double-Rate Mode, Normalized 0.05 0.10 0.15 0.20 0.25 0.30 f FREQUENCY (NORMALIZED ADC Decimation Filter Pass-Band Ripple, Double-Rate Mode, 14 Normalized ADAU1381 0.45 0.50 0.9 1.0 0.35 0.40 ...

Page 18

... ADAU1381 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 15. DAC Interpolation Filter, 64× Oversampling, Normalized 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 0.05 0.10 0.15 0.20 0.25 FREQUENCY (NORMALIZED TO Figure 16. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling, Normalized –10 –20 – ...

Page 19

... SPEAKER OUTPUT POWER (mW) Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 0 –20 –40 –60 –80 –100 100 600 Figure 22. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply Rev. A| Page ADAU1381 1 10 100 SPEAKER OUTPUT POWER (mW) ...

Page 20

... PDN PDN IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF 0.1µF 0.1µF 0.1µF 0.1µF SPN SPP AOUTL AOUTR ADAU1381 CM 100nF GPIO DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK Figure 23. System Block Diagram with Differential Inputs Rev Page – 8Ω SPEAKER ...

Page 21

... SPN SPP AOUTL AOUTR ADAU1381 CM 100nF GPIO DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK Rev. A| Page ADAU1381 – 8Ω SPEAKER + OUT 100pF STEREO SINGLE-ENDED HEADPHONE OUTPUT 10kΩ 10kΩ LEFT_OUT 10Ω 220µF CM 10kΩ 100pF 10kΩ ...

Page 22

... IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF 0.1µF 0.1µF 0.1µF 0.1µF SPN SPP AOUTL LMIC/LMICN/MICD1 AOUTR LMICP ADAU1381 RMIC/RMICN/MICD2 RMICP CM GPIO BEEP DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 MCKI ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK MCKO PDN Figure 25. System Block Diagram with Single-Ended Stereo Line Inputs Rev Page – ...

Page 23

... GPIO DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 SERIAL DATA BCLK/GPIO2 LRCLK/GPIO3 ADDR1/CLATCH ADDR0/CDATA SYSTEM CONTROLLER SDA/COUT SCL/CCLK Rev. A| Page ADAU1381 8Ω SPEAKER OUT 100pF STEREO SINGLE-ENDED HEADPHONE OUTPUT 10kΩ LEFT_OUT 10Ω 220µF 10kΩ 100pF 10kΩ 10kΩ 10Ω 220µF ...

Page 24

... PLL. The PLL accepts inputs from 11 MHz to 20 MHz. The ADAU1381 is provided in a small, 32-lead × lead frame chip scale package (LFCSP) with an exposed bottom pad 30-ball (6 × 5 bump), 3.4 mm × 2.64 mm wafer level chip scale package (WLCSP) ...

Page 25

... The POR monitors the DVDDOUT pin and generates a reset signal whenever power is applied to SUPPLY POWER TO AVDD1 the chip. During the reset, the ADAU1381 is set to the default values documented in the register map (see the Control Register SUPPLY POWER Map section). ...

Page 26

... For more information, see the Sound Engine section POWER REDUCTION MODES Sections of the ADAU1381 chip can be turned on and off as needed to reduce power consumption. These include the ADCs, the DACs, and the PLL. In addition, some functions can be set in the registers to operate in power saving, normal, or enhanced performance operation. ...

Page 27

... Settings Clock source select 0: direct from MCKI pin (default) 1: PLL clock Input master clock 00: 256 × f (default) S frequency 01: 512 × 10: 768 × 11: 1024 × Core clock enable 0: core clock disabled (default) 1: core clock enabled ADAU1381 SOUND DACs PORTS ...

Page 28

... ADAU1381 Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Table 14. Base Sampling Rate Divisions for f Base Sampling Frequency Sampling Rate Scaling kHz /1 /0.5 S Table 15. Base Sampling Rate Divisions for f ...

Page 29

... Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock Core Clock Sampling Rate Divider 11.2896 MHz (1 × 256) (6 × 256) (4 × 256) (3 × 256) (2 × 256) (1.5 × 256) (0.5 × 256) Rev. A| Page ADAU1381 Sampling Rate 48 kHz 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz Sampling Rate 44.1 kHz 7.35 kHz 11 ...

Page 30

... ADC CM Figure 31. Record Signal Path Diagram INPUT SIGNAL PATH The ADAU1381 can be configured for three types of microphone inputs: single-ended, differential, or digital. The LMIC/LMICN/ MICD1 and RMIC/RMICN/MICD2 pins encompass all of these configurations. LMICP and RMICP are used only during differential configurations (see Figure 31, the record signal path diagram) ...

Page 31

... Bit 5, high-pass filter select, where it can be enabled or disabled. DIGITAL DUAL-BAND AUTOMATIC LEVEL CONTROL (ALC) The ADAU1381 includes an automatic level control (ALC). The ALC adjusts the input gain continuously for a varying input signal as dictated by the user-defined ALC settings. This allows the input recording level to remain constant ...

Page 32

... MIXER Figure 35. Playback Signal Path Diagram OUTPUT SIGNAL PATHS The outputs of the ADAU1381 include a left and right line output and speaker driver. The beep input signal can be mixed into any of these outputs, with separate gain control for each path. DIGITAL-TO-ANALOG CONVERTERS The ADAU1381 uses two 24-bit Σ ...

Page 33

... ADAU1381 and the system mode, the ADAU1381 is always a slave on the bus, meaning it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address byte format is shown in Table 21. The address resides in the first seven bits of the I LSB of this byte sets either a read or write operation ...

Page 34

... SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register acknowledge is issued by the ADAU1381, and the part returns to the idle condition. R/W ...

Page 35

... Figure 41 shows the timing of a burst mode write sequence. This figure shows an example where the target destination registers are two bytes. The ADAU1381 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length ...

Page 36

... Figure 4 . All data should be written MSB first. The ADAU1381 can be taken out of SPI mode only by a full reset. Chip Address R/ W The first byte of an SPI transaction includes the 7-bit chip address and bit. The chip address is always 0x38. The LSB of this first byte determines whether the SPI transaction is a read (Logic write (Logic 0) ...

Page 37

... CLATCH CCLK CDATA BYTE 0 Figure 44. SPI Write to ADAU1381 Clocking (Single-Write Mode) CLATCH CCLK CDATA BYTE 0 HIGH-Z COUT Figure 45. SPI Read from ADAU1381 Clocking (Single-Read Mode) BYTE 1 BYTE 1 BYTE 3 DATA Rev. A| Page ADAU1381 BYTE 2 BYTE 3 HIGH-Z DATA ...

Page 38

... The ADAU1381 TDM implementation is a TDM audio stream. Unlike a true TDM bus, its output does not become high imped- ance during periods when it is not transmitting data. In TDM 8 mode, the ADAU1381 can be a master for f 48 kHz. Table 25 lists the modes in which the serial output port can function. ...

Page 39

... LRCLK BCLK MSB MSB – 1 MSB – 2 DATA Figure 50. TDM Mode SLOT 2 SLOT 3 SLOT 4 SLOT 5 Figure 51. TDM Mode with Pulse Word Clock Rev. A| Page ADAU1381 LSB RIGHT CHANNEL LSB RIGHT CHANNEL MSB LSB SLOT 7 SLOT 8 MSB TDM 8TH CH SLOT 6 SLOT 7 ...

Page 40

... ADAU1381 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the general- purpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial data/GPIO pin configuration. The GPIO pins can be used as either inputs or outputs. These pins are readable and can be set either through the control interface or directly by the sound engine ...

Page 41

... SOUND ENGINE SIGNAL PROCESSING The ADAU1381 is designed to provide a fixed-function signal processing flow specifically catered to digital still cameras and other low power applications. PROCESSING FLOW The processing flow is outlined in Figure 52. PROGRAMMING Although the sound engine’s audio processing flow is fixed- function, processing parameters and signal paths can be modified by the user ...

Page 42

... AVDD1 pin (up to 300 mA). An appro- priately thick trace is recommended. EXPOSED PAD PCB DESIGN The ADAU1381 LFCSP package has an exposed pad on the underside. This pad is used to couple the package to the PCB for heat dissipation when using the outputs to drive earpiece or headphone loads ...

Page 43

... Dejitter control Digital Power-Down 0 Digital Power-Down 1 GPIO pin control GPIO pin value registers Nonmodulo registers Sound engine frame rate Serial input route control Serial output route control Serial data/GPIO pin configuration Sound engine run Serial port sampling rate Rev. A| Page ADAU1381 ...

Page 44

... Register 16384 (0x4000), Clock Control The clock control register sets the clocking scheme for the ADAU1381. The system clock can be generated from either the PLL or directly from the MCKI (master clock input) pin. Addi- tionally, the MCKO (master clock output) pin can be configured. ...

Page 45

... PLL has locked to the input master clock. Bit 0, PLL Enable This bit enables the PLL. Description Reserved Regulator output level 00: 1.5 V 01: 1.4 V 10: 1.6 V 11: 1.7 V Reserved Rev. A| Page ADAU1381 is 48 kHz, then the PLL clock is 49.152 MHz S ; therefore, S Default 01 ...

Page 46

... ADAU1381 Table 32. PLL Control Register Bits Description [47:40] Denominator MSB 00000000 and 00000000: M[15:8] and M[7: … 00000000 and 11111101: M[15:8] and M[7:0] = 125 … 11111111 and 11111111: M[15:8] and M[7:0] = 65,535 [39:32] Denominator LSB 00000000 and 00000000: M[15:8] and M[7: … 00000000 and 11111101: M[15:8] and M[7:0] = 125 … 11111111 and 11111111: M[15:8] and M[7:0] = 65,535 ...

Page 47

... Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz Integer (R) Denominator (M) 4 125 3 1625 205 2 825 Rev. A| Page ADAU1381 Numerator (N) 477 3849 17 44 302 386 Numerator (N) 12 1269 31 14 102 398 ...

Page 48

... ADAU1381 RECORD PATH CONFIGURATION Register 16392 (0x4008), Digital Microphone and Analog Beep Control This register controls the digital microphone settings and the analog beep input gain. Bits[5:4], Digital Microphone Enable These bits control the enable function for the stereo digital microphones. The analog front end is powered down when using a digital microphone ...

Page 49

... Bits[4:3], ADC Bias Control These bits set the bias current for the ADCs based on the mode of operation selected. Bits[2:1], Front-End Bias Control These bits set the bias current for the PGAs and mixers in the front-end record path. Rev. A| Page ADAU1381 Default ...

Page 50

... ADAU1381 Register 16398 (0x400E), Record Gain Left PGA The record gain left PGA control register controls the left channel input PGA. This register configures the input for either differ- ential or single-ended signals and sets the left channel input recording volume. Bits[7:5], Left Input Gain These bits set the left channel analog microphone input PGA gain ...

Page 51

... PGA is switched to common mode. Bit 1, Record Path Right Mute This bit mutes the entire right channel input PGA. Bit 0, Right PGA Enable This bit enables the right channel PGA. Rev. A| Page ADAU1381 Default 000 ...

Page 52

... ADAU1381 Register 16400 (0x4010), Microphone Bias Control and Beep Enable Bit 4, Beep Input Enable This bit enables the beep signal, which is input to the BEEP pin. Setting this bit to 0 mutes the beep signal for all output paths. Bit 3, Microphone High Performance This bit puts the microphone bias into high performance mode, by offering more current to the microphone ...

Page 53

... Within a TDM stream, channels are grouped by pair, as shown in Figure 60. Bit 0, Serial Data Port Mode This bit sets the clock pins as either master or slave. Both LRCLK and BCLK are the bus master of the serial port when master mode is enabled. Rev. A| Page ADAU1381 Default ...

Page 54

... ADAU1381 BCLK POLARITY LRCLK BCLK SDATA LRCLK BCLK SDATA LRCLK POLARITY LRCLK LRCLK LRCLK STEREO CHANNELS TDM 4 CHANNELS TDM 8 CHANNELS 1 LRCLK TDM 4 CHANNELS FIRST PAIR 1 TDM 8 CHANNELS Figure 57. Serial Port BCLK Polarity Figure 58. Serial Port LRCLK Polarity f 1/ LRCLK ...

Page 55

... Figure 67 shows an example of delay by 16 for a 16-bit audio stream with 64 BCLK cycles per frame. Rev. A| Page ADAU1381 2 S standard is a delay of one BCLK Default 000 ...

Page 56

... ADAU1381 LRCLK BCLK LRCLK BCLK LRCLK TDM 4 CHANNELS FIRST PAIR LEFT TDM 8 CHANNELS LRCLK TDM 4 CHANNELS FIRST PAIR TDM 8 CHANNELS ...

Page 57

... Figure 67. Serial Audio Data Delay by 16 Example Rev. A| Page ADAU1381 ...

Page 58

... ADAU1381 AUDIO CONVERTER CONFIGURATION Register 16407 (0x4017), Converter Control 0 Bits[6:5], On-Chip DAC Data Selection in TDM Mode These bits set the position of the DAC input channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair. In TDM 8 mode, valid settings are first pair, second pair, third pair, or fourth pair ...

Page 59

... Figure 70. Example of Left Channel First, Fourth Pair TDM Setting f 1/ LRCLK SECOND PAIR RIGHT SECOND PAIR THIRD PAIR f 1/ LRCLK SECOND PAIR RIGHT SECOND PAIR THIRD PAIR RIGHT LEFT f 1/ LRCLK SECOND PAIR THIRD PAIR Rev. A| Page ADAU1381 FOURTH PAIR LEFT FOURTH PAIR FOURTH PAIR LEFT RIGHT ...

Page 60

... ADAU1381 Register 16408 (0x4018), Converter Control 1 Bits[1:0], On-Chip ADC Data Selection in TDM Mode These bits set the position of the ADC output channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair. In TDM 8 mode, valid settings are first pair, second pair, third pair, or fourth pair ...

Page 61

... This bit must be configured accordingly to recognize a valid output state of the microphone. The default is negative, meaning that a digital logic low signal is recognized by the ADAU1381 as a pulse in the PDM signal. Table 44. ADC Control Register ...

Page 62

... ADAU1381 Register 16410 (0x401A), Left ADC Attenuator Bits[7:0], Left ADC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process ...

Page 63

... The gain control increments and should not be incremented more than time in order to avoid audible artifacts on the output. Rev. A| Page ADAU1381 Default 0 0000 Default ...

Page 64

... ADAU1381 Register 16415 (0x401F), Playback Mono Mixer Control Bit 7, Left DAC Mute This bit mutes the left DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bit 6, Right DAC Mute This bit mutes the right DAC output, but does not power down the DAC ...

Page 65

... Right line output mute (active low) 0: muted 1: unmuted 0 Reserved Register 16422 (0x4026), Right Line Output Mute Bit 1, Right Line Output Mute This bit mutes the right line output. It does not have any effect on the speaker outputs. Rev. A| Page ADAU1381 Default 0 Default 0 ...

Page 66

... ADAU1381 Register 16423 (0x4027), Playback Speaker Output Control Bits[7:6], Speaker Output Gain Control These bits control the gain of the speaker output. In general, this parameter should be tuned at a system level, set once during system initialization and not altered during operation of the system. ...

Page 67

... These bits control the amount of unity bias current allotted to the playback mixers and amplifiers. Bit 1, Back-End Right Enable This bit enables the playback mixers and amplifiers. Bit 0, Back-End Left Enable This bit enables the playback mixers and amplifiers. Rev. A| Page ADAU1381 Default ...

Page 68

... ADAU1381 Register 16426 (0x402A), DAC Control Bits[7:6], Mono Mode These bits control the output mode of the DAC. Setting these bits to 00 outputs two distinct channels, left and right. Setting these bits to 01 outputs the left input channel on both the left and right outputs, and the right input channel is lost. Setting these bits to 10 outputs the right input channel on both the left and right outputs, and the left input channel is lost ...

Page 69

... When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process. The slew ramp is logarithmic, incrementing 0.375 dB per audio frame. Rev. A| Page ADAU1381 Default 00000000 Default 00000000 ...

Page 70

... ADAU1381 PAD CONFIGURATION Figure 71 shows a block diagram of the pad design for the GPIO/serial port and communications port pins. OUTPUT ENABLE OUTPUT PULL-UP ENABLE (CONTROLS PMOS) DEBOUNCE ENABLE DATA IN DEBOUNCE WEAK PULL-UP ENABLE WEAK PULL-DOWN ENABLE DRIVE STRENGTH (CONTROLS NUMBER OF PARALLEL TRANSISTOR PAIRS) IOVDD = 3.3V ...

Page 71

... The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[1:0], BCLK Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Rev. A| Page ADAU1381 Default ...

Page 72

... ADAU1381 Register 16430 (0x402E), Serial Port Pad Control 1 Bit 3, ADC_SDATA Pin Drive Strength This bit sets the drive strength of the ADC_SDATA pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3 1.5 mA when IOVDD = 1.8 V. Bit 2, DAC_SDATA Pin Drive Strength This bit sets the drive strength of the DAC_SDATA pin ...

Page 73

... The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[1:0], SDA/COUT Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Rev. A| Page ADAU1381 Default ...

Page 74

... ADAU1381 Register 16432 (0x4030), Communication Port Pad Control 1 Bit 3, CDATA Pin Drive Strength This bit sets the drive strength of the CDATA pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3 1.5 mA when IOVDD = 1.8 V. Bit 2, CLATCH Pin Drive Strength This bit sets the drive strength of the CLATCH pin ...

Page 75

... This bit enables or disables a weak pull-up device on the pad. The effective resistance of the pull-up is nominally 240 kΩ. Bit 0, MCKO Pull-Down Enable This bit enables or disables a weak pull-down device on the pad. The effective resistance of the pull-down is nominally 240 kΩ. Rev. A| Page ADAU1381 Default ...

Page 76

... ADAU1381 Register 16434 (0x4032), Dejitter Control Bits[7:0], Dejitter Window Size The dejitter control register not only allows the size of the dejitter window to be set, but also allows all dejitter circuits in the device to be activated or bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode. Disabling and reenabling certain subsystems in the device— ...

Page 77

... Setting this bit to 0 disables the internal clock generator, which generates all master clocks for the serial ports, sound engine, ADCs, and DACs. This bit must be enabled if audio is being passed through the ADAU1381. Bit 0, Sound Engine Setting this bit to 0 disables the sound engine and makes the memory inaccessible ...

Page 78

... ADAU1381 Register 16513 (0x4081), Digital Power-Down 1 Bit 3, Output Precharge The output precharge system allows the outputs to be biased before they are enabled and prevents pops or clicks from appearing on the output. This bit should be set all times. Bit 2, Zero-Crossing Detector Setting this bit to 0 disables the zero-crossing detector for beep playback ...

Page 79

... C/SPI port with pull-up 2 C/SPI port without pull-up Register GPIO pin value, GPIO GPIO pin value, GPIO0 GPIO pin value, GPIO1 GPIO pin value, GPIO2 GPIO pin value, GPIO3 Rev. A| Page ADAU1381 2 C/SPI port). Default 1100 1100 1100 1100 1100 ...

Page 80

... ADAU1381 Register 16617 and Register 16618 (0x40E9 and 0x40EA), Nonmodulo These registers set the boundary for the nonmodulo RAM space used by the sound engine. An appropriate value is automatically loaded to this register during initialization. It should not be modified for any reason. Table 70. Nonmodulo Registers ...

Page 81

... L0] to DACs [L, R] 1010: reserved 1 1011: serial input [R1, L1] to DACs [L, R] 1100: reserved 1 1101: serial input [R2, L2] to DACs [L, R] 1110: reserved 1 1111: serial input [R3, L3] to DACs [ left side of Channel right side of Channel x. Rev. A| Page ADAU1381 Default 0000 ...

Page 82

... ADAU1381 Register 16627 (0x40F3), Serial Output Route Control Bits[3:0], Output Routing These bits select where the ADC outputs are routed in the serial data stream (see Figure 72). Table 73. Serial Output Route Control Register Bits Description [7:4] Reserved [3:0] Output routing 0000: ADCs to sound engine to serial outputs ...

Page 83

... These bits set the serial port sampling rate as a function of the audio sampling rate most applications, the serial port S sampling rate, sound engine sampling rate, and ADC and DAC sampling rates should be equal. Rev. A| Page ADAU1381 Default Default ...

Page 84

... ADAU1381BCPZ-RL −25°C to +85°C ADAU1381BCPZ-RL7 −25°C to +85°C ADAU1381BCBZ-RL −25°C to +85°C ADAU1381BCBZ-RL7 −25°C to +85°C EVAL-ADAU1381Z RoHS Compliant Part. Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I ...

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