adau1381 Analog Devices, Inc., adau1381 Datasheet - Page 74
adau1381
Manufacturer Part Number
adau1381
Description
Low-noise Stereo Codec With Enhanced Recording And Playback Processing
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADAU1381.pdf
(84 pages)
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ADAU1381
Register 16432 (0x4030), Communication Port Pad
Control 1
Bit 3, CDATA Pin Drive Strength
This bit sets the drive strength of the CDATA pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
Bit 2, CLATCH Pin Drive Strength
This bit sets the drive strength of the CLATCH pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Table 62. Communication Port Pad Control 1 Register
Bits
[7:4]
3
2
1
0
Description
Reserved
CDATA pin drive strength
0: low
1: high
CLATCH pin drive strength
0: low
1: high
SCL/CCLK pin drive strength
0: low
1: high
SDA/COUT pin drive strength
0: low
1: high
Rev. A | Page 74 of 84
Bit 1, SCL/CCLK Pin Drive Strength
This bit sets the drive strength of the SCL/CCLK pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Bit 0, SDA/COUT Pin Drive Strength
This bit sets the drive strength of the SDA/COUT pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Default
0
0
0
0
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