adau1381 Analog Devices, Inc., adau1381 Datasheet - Page 43

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adau1381

Manufacturer Part Number
adau1381
Description
Low-noise Stereo Codec With Enhanced Recording And Playback Processing
Manufacturer
Analog Devices, Inc.
Datasheet

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CONTROL REGISTER MAP
All registers except the PLL control register are 1-byte write and read registers.
Table 27.
Hex
0x4000
0x4001
0x4002
0x4008
0x4009
0x400E
0x400F
0x4010
0x4015
0x4016
0x4017
0x4018
0x4019
0x401A
0x401B
0x401C
0x401E
0x401F
0x4020
0x4025
0x4026
0x4027
0x4028
0x4029
0x402A
0x402B
0x402C
0x402D
0x402E
0x402F
0x4030
0x4031
0x4032
0x4080
0x4081
0x40C6 to 0x40CA
0x03E8 to 0x03EC
0x40E9 to 0x40EA
0x40EB
0x40F2
0x40F3
0x40F4
0x40F6
0x40F8
Address
Decimal
16384
16385
16386
16392
16393
16398
16399
16400
16405
16406
16407
16408
16409
16410
16411
16412
16414
16415
16416
16421
16422
16423
16424
16425
16426
16427
16428
16429
16430
16431
16432
16433
16434
16512
16513
16582 to 16586
1000 to 1004
16617 to 16618
16619
16626
16627
16628
16630
16632
Name
Clock control
Regulator control
PLL control (48-bit register)
Digital microphone and analog beep control
Record power management
Record gain left PGA
Record gain right PGA
Microphone bias control and beep enable
Serial Port Control 0
Serial Port Control 1
Converter Control 0
Converter Control 1
ADC control
Left ADC attenuator
Right ADC attenuator
Playback mixer left control
Playback mixer right control
Playback mono mixer control
Playback clamp amplifier control
Left line output mute
Right line output mute
Playback speaker output control
Beep zero-crossing detector control
Playback power management
DAC control
Left DAC attenuator
Right DAC attenuator
Serial Port Pad Control 0
Serial Port Pad Control 1
Communication Port Pad Control 0
Communication Port Pad Control 1
MCKO control
Dejitter control
Digital Power-Down 0
Digital Power-Down 1
GPIO pin control
GPIO pin value registers
Nonmodulo registers
Sound engine frame rate
Serial input route control
Serial output route control
Serial data/GPIO pin configuration
Sound engine run
Serial port sampling rate
Rev. A| Page 43 of 84
ADAU1381

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