isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 100

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 89:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcDMACounter register: bit allocation
R/W
R/W
15
0
7
0
13.1.7 DcDMACounter Register (R/W: F3H/F2H)
Table 88:
For selecting an endpoint for device DMA transfer, see
This command accesses the DcDMACounter register. The bit allocation is given in
Table
the register returns the number of remaining bytes in the current transfer. A bus reset
will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DcDMACounter register
when DMA is re-enabled (DMAEN = 1). See
Code (Hex): F2/F3 — write/read DcDMACounter register
Transaction — write/read 1 word
Bit
15
14
13 to 8
7 to 4
3
2
1 to 0
R/W
R/W
14
0
6
0
89. Writing to the register sets the number of bytes for a DMA transfer. Reading
DcDMAConfiguration register: bit description
Symbol
CNTREN
SHORTP
-
EPDIX[3:0]
DMAEN
-
BURSTL[1:0]
R/W
R/W
13
0
5
0
Rev. 02 — 13 December 2002
Description
Logic 1 enables the generation of an EOT condition, when the
DcDMACounter register reaches zero. Bus reset value:
unchanged.
Logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
reserved
Indicates the destination endpoint for DMA, see
Writing logic 1 enables DMA transfer, logic 0 forces the end of
an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit
is cleared by a bus reset.
reserved
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
Full-speed USB single-chip host and device controller
R/W
R/W
12
0
4
0
DMACR[15:8]
DMACR[7:0]
R/W
R/W
11
0
3
0
Section 13.1.6
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Section
for more details.
11.2.
R/W
R/W
9
0
1
0
ISP1161
Table
71.
100 of 137
R/W
R/W
8
0
0
0