isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 48

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 12:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcCommandStatus register: bit allocation
31
23
15
0
7
0
10.1.3 HcCommandStatus register (R/W: 02H/82H)
The HcCommandStatus register is used by the HC to receive commands issued by
the HCD, and it also reflects the HC’s current status. To the HCD, it appears to be a
‘write to set’ register. The HC must ensure that bits written as logic 1 become set in
the register while bits written as logic 0 remain unchanged in the register. The HCD
may issue multiple distinct commands to the HC without concern for corrupting
previously issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount field indicates the number of frames with which the HC
has detected the scheduling overrun error. This occurs when the Periodic list does
not complete before EOF. When a scheduling overrun error is detected, the HC
increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus
register.
Code (Hex): 02 — read
Code (Hex): 82 — write
30
22
14
0
6
0
29
21
13
0
5
0
Rev. 02 — 13 December 2002
reserved
R
reserved
Full-speed USB single-chip host and device controller
28
20
12
0
4
0
reserved
reserved
00H
00H
R/W
R/W
R
27
19
11
0
3
0
26
18
10
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
25
17
0
9
1
0
ISP1161
SOC[1:0]
R
HCR
48 of 137
24
16
0
8
0
0