isp1505a NXP Semiconductors, isp1505a Datasheet - Page 48

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 23.
Table 24.
ISP1505A_ISP1505C_1
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_SUSPENDM
-
3PIN_FSLS_SERIAL
6PIN_FSLS_SERIAL
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description
OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation
USE_EXT_
VBUS_IND
10.1.4 OTG Control register
R/W/S/C
7
0
This register controls various OTG functions of the ISP1505. The bit allocation of the OTG
Control register is given in
VBUS_EXT
R/W/S/C
DRV_
6
0
Description
Interface Protect Disable: Controls circuitry built into the ISP1505 to protect the ULPI
interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the
ISP1505 will automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1505 attaches a weak
pull-up resistor on STP. If STP is unexpectedly HIGH, the ISP1505 attaches weak
pull-down resistors on DATA[7:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on
DATA[7:0], and a weak pull-up resistor on STP.
Indicator Pass-through: The ISP1505 does not support the qualification of an external
FAULT with the internal V
V
must always be set to logic 1.
0b — Not supported.
1b — The complement output signal is not qualified with the internal A_VBUS_VLD
comparator. The link must always set this bit to logic 1.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating
the complement output. For details, see
0b — The ISP1505 will not invert the FAULT signal (default).
1b — The ISP1505 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in
6-pin serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set
to logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode.
1b — Clock will be powered in 3-pin and 6-pin serial modes.
reserved
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial
interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial
interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.
BUS
/FAULT pin or the V
R/W/S/C
DRV_
VBUS
5
0
Rev. 01 — 19 October 2006
Table
R/W/S/C
CHRG_
VBUS
BUS
A_VBUS_VLD
4
0
24.
power is connected to the V
DISCHRG_
ULPI HS USB host and peripheral transceiver
R/W/S/C
comparator. Either a digital FAULT is input on the
VBUS
3
0
Section
ISP1505A; ISP1505C
9.5.2.2.
DM_PULL
R/W/S/C
DOWN
2
1
BUS
/FAULT pin, not both. This bit
DP_PULL
R/W/S/C
DOWN
1
1
© NXP B.V. 2006. All rights reserved.
reserved
R/W/S/C
0
0
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