isp1505a NXP Semiconductors, isp1505a Datasheet - Page 64

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1505A_ISP1505C_1
Product data sheet
Fig 21. Rise time and fall time
Fig 23. Timing of TX_ENABLE to DP and DM
1.8 V
V
V
V
V
0 V
OH
OH
OL
OL
logic
input
differential
data lines
0.9 V
t
HSR
10 %
15.1 ULPI timing
, t
FR
t
V
t
PZH
PZL
CRS
, t
LR
90 %
ULPI interface timing requirements are given in
synchronous mode only. All timing is measured with respect to the ISP1505 CLOCK pin.
All signals are clocked on the rising edge of CLOCK.
Fig 25. ULPI timing interface
CONTROL OUT
CONTROL IN
(DIR, NXT)
DATA OUT
DATA IN
CLOCK
V
V
(8-BIT)
(8-BIT)
OH
90 %
(STP)
OL
+ 0.3 V
t
0.3 V
HSF
t
t
PHZ
0.9 V
PLZ
10 %
, t
FF
, t
LF
Rev. 01 — 19 October 2006
t
su(DATA)
t
su(STP)
004aaa861
004aaa574
t
t
h(STP)
h(DATA)
Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM
Fig 24. Timing of DP and DM to RX_RCV, RX_DP and
1.8 V
differential
data lines
V
V
0 V
logic input
OH
OL
logic output
0.8 V
2.0 V
V
V
differential
data lines
OH
ULPI HS USB host and peripheral transceiver
OL
RX_DM
0.9 V
ISP1505A; ISP1505C
V
t
t
CRS
Figure
t
d(DIR)
d(NXT)
d(DATA)
t
PLH(drv)
,
V
t
t
PLH(se)
PLH(rcv)
CRS
25. This timing applies to
0.9 V
t
t
d(DIR)
d(NXT)
,
© NXP B.V. 2006. All rights reserved.
t
PHL(drv)
0.9 V
t
t
V
PHL(rcv)
PHL(se)
CRS
V
004aaa575
004aaa722
004aaa573
CRS
0.9 V
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