isp1562 NXP Semiconductors, isp1562 Datasheet - Page 44

• Manufacturer Part Number: isp1562
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 60.
Address: Content of the base address register + 20h
Table 61.
Address: Content of the base address register + 24h
Table 62.
Address: Content of the base address register + 24h
ISP1562_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 4 CHED[27:0]
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Symbol
reserved
Symbol
CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving the present. The Host
reserved
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description
11.1.10 HcControlCurrentED register
31
23
15
R
R
R
R
R
7
0
0
0
0
7
0
Description
Control Head ED: The Host Controller traverses the control list, starting with the HcControlHeadED
pointer. The content is loaded from HCCA during the initialization of the Host Controller.
-
Description
Controller must continue processing the list from where it left off in the last frame. When it reaches
the end of the control list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If set, it
copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does
nothing. The HCD is allowed to modify this register only when CLE (bit 4 in the HcControl register)
is cleared. When set, the HCD only reads the instantaneous value of this register. Initially, this is set
to logic 0 to indicate the end of the control list.
-
The HcControlCurrentED register contains the physical address of the current ED of the
control list. The bit allocation is given in
30
22
14
R
R
R
R
R
6
0
0
0
0
6
0
CHED[3:0]
CCED[3:0]
29
21
13
R
R
R
R
R
5
0
0
0
0
5
0
Rev. 02 — 1 March 2007
28
20
12
R
R
R
R
R
4
0
0
0
0
4
0
CCED[27:20]
CCED[19:12]
CCED[11:4]
Table
27
19
11
R
R
R
R
R
3
0
0
0
0
3
0
61.
26
18
10
R
R
R
R
R
2
0
0
0
0
2
0
HS USB PCI Host Controller
reserved
reserved
25
17
R
R
R
R
R
1
0
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1562
24
16
R
R
R
R
R
0
0
0
0
8
0
0
0
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