isp1562 NXP Semiconductors, isp1562 Datasheet - Page 54

• Manufacturer Part Number: isp1562
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 84.
Address: Content of the base address register + 50h
ISP1562_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30 to 18 reserved
17
16
15
14 to 2
1
0
The reserved bits should always be written with the reset value.
Symbol
CRWE
CCIC
LPSC
DRWE
reserved
OCI
LPS
HcRhStatus - Host Controller Root Hub Status register bit description
DRWE
R/W
R/W
R/W
23
15
0
0
7
0
Description
On write Clear Remote Wake-up Enable:
0 — No effect
1 — Clears DRWE (Device Remote Wake-up Enable).
-
Overcurrent Indicator Change: This bit is set by hardware when a change has occurred to the OCI
bit of this register.
0 — No effect
1 — The HCD clears this bit.
On read Local Power Status Change: The root hub does not support the local power status feature.
Therefore, this bit is always logic 0.
On write Set Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to
this bit to turn on power to all ports (clear Port Power Status). In per-port power mode, it sets Port
Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no effect.
On read Device Remote Wake-up Enable: This bit enables bit Connect Status Change (CSC) as a
resume event, causing a state transition from USBSUSPEND to USBRESUME and setting the
Resume Detected interrupt.
0 — CSC is not a remote wake-up event.
1 — CSC is a remote wake-up event.
On write Set Remote Wake-up Enable: Writing logic 1 sets DRWE (Device Remote Wake-up
Enable). Writing logic 0 has no effect.
-
Overcurrent Indicator: This bit reports overcurrent conditions when global reporting is implemented.
When set, an overcurrent condition exists. When cleared, all power operations are normal. If the
per-port overcurrent protection is implemented, this bit is always logic 0.
On read Local Power Status: The root hub does not support the local power status feature.
Therefore, this bit is always read as logic 0.
On write Clear Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to
this bit to turn off power to all ports (clear Port Power Status). In per-port power mode, it clears Port
Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no effect.
R/W
R/W
R/W
22
14
0
0
6
0
R/W
R/W
R/W
21
13
0
0
5
0
reserved
reserved
Rev. 02 — 1 March 2007
[1]
[1]
R/W
R/W
R/W
20
12
0
0
4
0
reserved
R/W
R/W
R/W
19
11
0
0
3
0
[1]
R/W
R/W
R/W
18
10
0
0
2
0
HS USB PCI Host Controller
CCIC
R/W
R/W
OCI
17
R
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1562
LPSC
R/W
R/W
LPS
RW
16
0
8
0
0
0
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