sta002 STMicroelectronics, sta002 Datasheet - Page 23

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

Reg name: PRC_TRSH2
Internal address: 203 H
Type: R/W
Reset Value: 23H
Description: Prime rate channel preamble recog-
nition - Warning flag threshold level.
It defines the minimum number of PRC preamble
bits to be recognized before setting an alarm con-
dition.
Reg name: PRC_ALARM
Internal address: 208 H
Type: R/W
Reset Value: 00H
Description: PRC finite state machine control reg-
ister (see table 5).
Reg name: PRC_ACTIVE_REG
Internal address: 20F H
Type: R
Table 5: PRC_ALARM
MSB
MSB
b7
b7
X
X
X
0
0
0
0
1
0
0
0
0
1
-
-
b6
X
b6
X
X
0
0
0
0
1
0
0
0
0
1
-
-
b5
b5
b5
X
X
0
0
1
1
1
0
0
1
1
1
-
-
b4
b4
b4
X
X
0
1
0
1
1
0
1
0
1
1
-
-
b3
X
b1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
b2
X
b0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
b1
b1
prcp_detection, prcp_presync, prcp_sync
prcp_detection, prcp_presync, prcp_sync, alarm 1
sp_detection, sp_presync, sp_sync, alarm2
sp_detection, sp_presync, sp_sync, alarm2 (1 cycle)
sp_detection, sp_presync, sp_sync, alarm2 (2 cycles)
sp_detection, sp_presync, sp_sync, alarm2 (3 cycles)
sp_detection, sp_presync, sp_sync, alarm2 (n cycles)
sp_detection, sp_presync, sp_sync, alarm2 (16 cycles)
sp_detection, sp_presync, sp_sync, alarm1, alarm2
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (1 cycle)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (2 cycles)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (3 cycles)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (n cycles)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (16 cycles)
LSB
LSB
b0
b0
Description: It gives the list of active PRC within
one selected BC.
b0 to b7 indicates PRC0 to PRC7 respectively.
Reg name: PRC_LOCK_REG
Internal address: 210 H
Type: R
Description: Lock status of each PRC
b0 to b7 indicates the lock status of PRC0 to
PRC7 respectively.
Reg name: PRC_DELAY_REG
Internal address: 211 H
Type: R
Description: PRC maximum number of delay
symbols
It detects the maximum number of delay symbols
among the PRC within the same BC.
MSB
MSB
MSB
b7
b7
X
PRC FSM active states
b6
b6
X
b5
b5
X
b4
b4
X
b3
b3
b3
b2
b2
b2
b1
b1
b1
STA002
LSB
LSB
LSB
23/43
b0
b0
b0