sta002 STMicroelectronics, sta002 Datasheet - Page 30

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

STA002
b3: Test purpose (must be set at 0 in functional
mode)
b7 to b4: test purpose
Reg name: BC_ALARM_REG
Internal address: 01CH
Type: R/W
Default:20H
Description: BC finite state machine control regis-
ter (see table 6)
b5 indicates the BC synchronization mode
1: SP preamble detection
0: Synch from PRC
Reg name: IW_REG
Internal address: 017, 016, 015, 014,
Type: W
IW_REG (63:56) (addr 017)
IW_REG (55:48) (addr 016)
Table 6: BC_ALARM_REG
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MSB
MSB
MSB
b2b1 =
b63
b55
X
b4
0
1
1
1
1
1
1
1
b62
b54
X
00
01
10
11
b3
0
0
0
0
0
1
1
-
b61
b53
b5
BC input delay (bytes)
1
2
3
4
013, 012, 011, 010,
b2
0
0
0
0
0
1
1
-
b60
b52
b4
b59
b51
b1
b3
0
0
0
1
1
1
1
-
b58
b50
b2
b0
0
0
1
0
1
0
1
-
b57
b49
b1
sp_detection, sp_presync, sp_sync
sp_detection, sp_presync, sp_sync, alarm_state (1 cycle)
sp_detection, sp_presync, sp_sync, alarm_state (2 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (3 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (4 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (n cycles)
sp_detection, sp_presync, sp_sync, alarm_state (15 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (16 cycles)
LSB
LSB
LSB
b56
b48
b0
IW_REG (47:40) (addr 015)
IW_REG (39:32) (addr 014)
IW_REG (31:24) (addr 013)
IW_REG (23:16) (addr 012)
IW_REG (15:8) (addr 011H)
IW_REG (7:0) (addr 010H)
Description:
b63 to b0 contain the initialization word IW.
MSB
MSB
MSB
MSB
MSB
MSB
b47
b39
b31
b23
b15
b7
BC FSM active states
b46
b38
b30
b22
b14
b6
b45
b37
b29
b21
b13
b5
b44
b36
b28
b20
b12
b4
b43
b35
b27
b19
b11
b3
b42
b34
b26
b18
b10
b2
b41
b33
b25
b17
b9
b1
LSB
LSB
LSB
LSB
LSB
LSB
b40
b32
b24
b16
b8
b0