at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 102

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Endpoint Reset
USB Reset
Endpoint Selection
102
AT85C51SND3B
At the end of the reset process (Full or High), the end of reset interrupt (EORSTI) is gen-
erated. Then the CPU should read the SPEED bit to know the speed mode of the
device.
Note that the USB device controller starts in the Full-speed mode after power on.
An endpoint can be reset at any time by setting in the UERST register the bit corre-
sponding to the endpoint (EPRSTx). This resets:
•
•
•
The data toggle field remains unchanged.
The other registers remain unchanged.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT
bit) as an answer to the CLEAR_FEATURE USB command.
When an USB reset is detected on the USB line, the next operations are performed by
the controller:
•
•
•
Prior to any operation performed by the CPU, the endpoint must first be selected. This is
done by:
•
•
The CPU can then access to the various endpoint registers and data.
In the same manner, if the endpoint must be accessed by the DFC, it must first be
selected. This is done by:
•
•
•
The DFC can then access to the banks (read / write).
The controller internally keeps in memory the EPNUM for the CPU and the EPNUM for
the DFC. In fact, there are 2 EPNUM registers multiplexed by the EPNUMS bit. Each of
them can be read or written by the CPU.
These two registers permits to easily switch from an endpoint under DFC data transfer
to the default control endpoint when a SETUP is received, without reprogramming the
EPNUM register:
the internal state machine on that endpoint,
the Rx and Tx banks are cleared and their internal pointers are restored,
the UEINTX, UESTA0X and UESTA1X are restored to their reset value.
all the endpoints are disabled, except the default control endpoint,
the default control endpoint is reset (see Section “Endpoint Reset” for more details).
The data toggle of the default control endpoint is cleared.
Clearing EPNUMS.
Setting EPNUM with the endpoint number which will be managed by the CPU.
Setting EPNUMS.
Setting EPNUM with the endpoint number which will be managed by the DFC.
Setting DFCRDY when the data-flow is ready to take place.
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–
–
–
–
Set EPNUMS,
EPNUM = endpoint
Set DFCRDY when the DFC transfer is ready to take place,
...<DFC transfer>...
SETUP received on endpoint
x
0
(EPINT0 set, RXSTPI set),
7632C–MP3–11/06