at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 221

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

7632C–MP3–11/06
Table 244. SFCON Register
SFCON (0.95h) – SIO Flow Control Register
Reset Value = 0000 0000b
Table 245. SINT Register
SINT (1.A8h) – SIO Interrupt Source Register
OVRSF3
Number
Number
7-4
1-0
Bit
Bit
7
3
2
7
7
6
5
4
3
2
-
Mnemonic Description
OVRSF3:0
Mnemonic Description
RTSTH1:0
OVRSF2
CTSEN
RTSEN
EOTI
OEI
PEI
FEI
Bit
Bit
6
6
-
-
-
Over Sampling Factor Bits
Number of time a data bit is sampled for level determination.
Oversampling factor = OVRSF3:0 + 1.
Clear To send Enable Bit
Set to enable transmission hardware flow control using CTS signal.
Clear to disable transmission hardware flow control.
Request To send Enable Bit
Set to enable reception hardware flow control using RTS signal.
Clear to disable reception hardware flow control.
Request To send Assertion Threshold
Refer to Table 242 for information on threshold values.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
End Of Transmission Interrupt Flag
Set by hardware when both Tx FIFO and Tx shift register are empty: actual end
of transmission.
Cleared by hardware when the Tx FIFO or Tx shift register are not empty.
Overrun Reception Error Interrupt Flag
Set by hardware when a character is received while the Rx shift register is full
(Rx FIFO full).
Clear by software to acknowledge interrupt.
Parity Reception Error Interrupt Flag
Set by hardware when a parity error occurs in a received character.
Clear by software to acknowledge interrupt.
Framing Reception Error Interrupt Flag
Set by hardware when a framing error occurs in a received character.
Clear by software to acknowledge interrupt.
OVRSF1
EOTI
5
5
OVRSF0
OEI
4
4
CTSEN
PEI
3
3
AT85C51SND3B
RTSEN
FEI
2
2
RTSTH1
TI
1
1
RTSTH0
RI
0
0
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