at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 23

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

7632C–MP3–11/06
Note:
Figure 10. Power-down Exit Waveform Using INT1:0
Figure 11. Power-down Exit Waveform Using KIN3:0
Note:
2. Generate a reset.
Notes:
KIN3:0
INT1:0
OSC
OSC
–
(1)
the clocks to the CPU and peripherals. Using INTn input, execution resumes
when the input is released (see Figure 10) while using KINx input, execution
resumes after counting 1024 clock ensuring the oscillator is restarted properly
(see Figure 11). This behavior is necessary for decoding the key while it is still
pressed. In both cases, execution resumes with the interrupt service routine.
Upon completion of the interrupt service routine, program execution resumes
with the instruction immediately following the instruction that activated Power-
down mode.
1. The external interrupt used to exit Power-down mode must be configured as level
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
1. KIN3:0 can be high or low-level triggered.
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-down mode and may
continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT85C51SND3B and vectors the CPU to address
0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
Active Phase
Active Phase
sensitive (
duration of the interrupt must be long enough to allow the oscillator to stabilize. The
execution will only resume when the interrupt is de-asserted.
RAM content.
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
RAM content.
INT0
Power-down Phase
Power-down Phase
and
INT1
) and must be assigned the highest priority. In addition, the
Oscillator Restart Phase
42000 clock count
AT85C51SND3B
Active Phase
Active Phase
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