at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 32

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

MMC Clock Generator
32
AT85C51SND3B
Figure 21. DFC/NFC Clock Generator Block Diagram and Symbol
Table 27. DFC/NFC Clock Selection
The MMC clock generator block diagram is shown in Figure 22 and is based on a fre-
quency selector followed by a frequency divider.
Frequency selection is done using MMCCKS2:0 bits in MMCCLK (see Table 35)
according to Table 28
Frequency division is done using MMCDIV4:0 bits in MMCCLK according to Table 29.
Frequency configuration (selection and division) must be done prior to enable the MMC
clock generation by setting MMCKEN bit in CKEN.
Note:
Figure 22. MMC Clock Generator Block Diagram and Symbol
CLOCK
GEN
DNFCKS2:0
1. To allow low frequency as low as 400 KHz (frequency needed in MMC identification
phase), F
000
001
010
100
101
011
110
111
CLOCK
GEN
OSC
OSC
(1)
60 MHz
48 MHz
30 MHz
24 MHz
20 MHz
16 MHz
selection can be divided by 2.
.
OSC
Clock Selection (F
F
60 MHz
48 MHz
40 MHz
30 MHz
24 MHz
20 MHz
16 MHz
OSC
÷
2
60 MHz
48 MHz
40 MHz
30 MHz
24 MHz
20 MHz
16 MHz
(default)
OSC
MMCCKS2:0
MMCCLK.7:5
000
001
010
011
100
101
110
111
DNFCKS2:0
CKSEL.7:5
000
001
010
011
100
101
110
111
S
)
F
S
F
S
MMCDIV4:0
MMCCLK.4:0
Divider
Clock
DFC/NFC Clock Symbol
DNFCKEN
CKEN.0
CLOCK
DNFC
MMCKEN
MMC Clock Symbol
CKEN.3
DFC Clock
NFC Clock
CLOCK
MMC
7632C–MP3–11/06
MMC Clock