saa6712e NXP Semiconductors, saa6712e Datasheet - Page 15

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.4
The TFT output port consists of two pixel ports (A and B),
each containing red, green and blue colour information
with a resolution of 8 bits per colour. The first pixel port is
mapped to PAR7 to PAR0, PAG7 to PAG0, and
PAB7 to PAB0. The second port is mapped to
PBR7 to PBR0, PBG7 to PBG0, and PBB7 to PBB0.
The vertical and horizontal synchronization signals are
mapped to pins PVS and PHS. A data validation signal
framing visible pixels is available at pin PDE.
All of the above mentioned signals are synchronized to the
output clock at pin PCLK. The active edge of this clock is
programmable.
7.4.1
The single pixel mode is designed to support TFT panels
with single pixel input, and for direct connection of panel
link transmitters. Only the first pixel port PAR7 to PAR0,
PAG7 to PAG0, and PAB7 to PAB0 is used. The data is
applied at double the frequency in comparison to the
double pixel output mode.
7.4.2
The double pixel mode is used for direct connection of TFT
panels with double pixel input. Both output ports are used.
The first pixel is applied at port A, and the second at port B.
7.5
The memory port connects the SAA6712E to the external
frame buffer. This frame memory can be built from either
1M
Supported are RAM devices with clock frequencies up to
1999 Aug 25
handbook, full pagewidth
XGA RGB to TFT graphics engine
16 SDRAM or 256k
TFT output port
Memory port
RGB data
S
D
CLAMP
INGLE PIXEL MODE
OUBLE PIXEL MODE
GAINC
VHS
32 SGRAM devices.
Fig.4 Clamp and gain correction pulses.
blanking
15
125 MHz. This clock can be provided either by the internal
PLL, or externally be applied to pin MCLKI.
The memory data bus is split into 4 ports:
port 0 (DQ0 to DQ15), port 1 (DQ16 to DQ31),
port 2 (DQ32 to DQ47) and port 3 (DQ48 to DQ63).
To adapt the external memory to the needs of the
application by means of memory size and bandwidth, it is
possible to scale the external memory by using only the
number of subsequent ports needed to build up the frame
buffer and to achieve the memory bandwidth. As a second
step for bandwidth optimization several speed grades of
memory devices can be used.
7.5.1
SDRAMs are available in sizes from 16 Mbits. For this
application a wide data bus is required, so that at least
1M
bandwidth, 2 to 4 devices must be used in parallel, which
results in a frame buffer size of 4 to 8 Mbytes. But only half
of this memory will be used by the SAA6712E.
The memory port of the SAA6712E can be divided into
4 SDRAM channels. Each channel is 16 bits wide, and
provides in High Speed Channel (HSC) mode with a
125 MHz memory clock and an effective bandwidth of
228 Mbits/s. A Medium Speed Channel (MSC) with a
100 MHz memory clock gives an effective bandwidth of
182 Mbits/s, 91% effective bandwidth assumed.
Table 2 gives the channel configuration for several input
and panel resolutions.
16 devices must be used. To achieve the desired
SDRAM
MEMORY CONFIGURATION
Preliminary specification
MHB244
SAA6712E