saa6703h NXP Semiconductors, saa6703h Datasheet - Page 15

• Manufacturer Part Number: saa6703h
• Description: Xga Dual Input Flat Panel Controller.
• Manufacturer: NXP Semiconductors

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Table 6 Global configuration registers
Table 7 General control configuration registers (page 0); note 1
Global control: FAH to FFH
GC_MISC0
GC_MISC1
GC_RESET
GC_INT_MASK
GC_INT_CLR
GC_INT_STAT
GC_PAGE
Device identification: 00H to 03H
DEV_ID_HI
DEV_ID_LO
IIC_TEST
IIC_MODE
Clock distribution: 10H to 12H
CD_CLK_EN
CD_CLK_AUTO
CD_CLK_MUX
Sync distribution: 18H and 19H
SYNC_SEL
REGISTER
REGISTER
FAH W
FBH W
FCH W
FEH R
FFH R/W
00H R
01H R
02H R/W 00H
03H W
10H W
18H W
ADR R/W
FDH W
FEH W
ADR R/W
11H W
12H W
00H
FFH
1FH
13H
1CH
0 0 0000
1 1 1111
0 0 0000
RESET
RESET
00 0000
11 0110
0 0000
0000
1111
00
avi_
noclamp_
sog_en
avi_
noclamp_
pol
dev_id[15:8]
dev_id[7:0]
iic_test[7:0]
D7
D7
dvi_lock_
sgnl_sel
reserved
int_iif_en
int_iif_clr
int_iif_stat
D6
D6
reserved
cfgclk_on
vclk_in_en cfgclk_
D5
D5
reset_
csdec_n
int_mode_
en
int_mode
int_mode
osd_
cfgclk_on
select
hs_regen_
in_en
D4
D4
reset_
dviclk
int_auto_
en
int_auto
int_auto
page_select[3:0]
aaclk_on
aaclk_auto dscclk_
fifo_fclk
vsync_out_
en
D3
D3
dvi_acc_
phase_diff
dvi_
delock_int_
mdd_en
reset_fclk
int_fifo_en
int_fifo
int_fifo
dscclk_on
auto
frontend_
bclk
cs_dvi_de
D2
D2
dvi_phase_adj_
threshold
reserved
reset_bclk
int_osd_en int_oif_en
int_osd
int_osd
iic_spike_mode[1:0]
uscclk_on
uscclk_
auto
bclk_in_en clk_div4
sog_out_
en
D1
D1
reset_oif
int_oif
int_oif
osdclk_on
osdclk_
auto
sog_en
D0
D0