saa6703h NXP Semiconductors, saa6703h Datasheet - Page 83

• Manufacturer Part Number: saa6703h
• Description: Xga Dual Input Flat Panel Controller.
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 56 Global modes; note 1
Note
1. X = don’t care.
7.17.8
The output interface can handle single and double pixel
mode (bit double_pixel in register OI_CTRL1). In single
pixel mode one pixel (24 bits) is available each cycle at the
output ports. The panel clock PCLK is the same as the
back-end clock. In double pixel mode 2 pixels (48 bits) are
available at the output ports. The PCLK in double pixel
mode changes every second cycle of the back-end clock.
The panel clock polarity can be inverted by setting
PCLK_pol of register OI_CTRL1 to logic 1. At the
beginning of each frame the PCLK is synced again. It is
very important that the number of pixels in a double pixel
frame is even.
The horizontal sync signal of the selected video input
sources (DVI or VGA) may be used as a reference clock
for the panel PLL (see Table 57). This allows more stable
locking of the panel timing to the source timing. In this
mode the PLL will be ‘coasted’ during vertical sync when a
composite sync or sync-on-green is enabled
(iif_cs_sog_en = 1).
Table 57 Panel PLL
7.17.9
Table 58 Starting output interface
2004 Apr 01
enable
XGA dual input flat panel controller
STEP
OI_
X
1
0
1
pll_src
1
2
3
4
5
0
1
P
H
ANEL CLOCK
OW TO START THE OUTPUT INTERFACE
power_
down
set-up frame geometry
set-up signal generators
set-up wait column and wait mode
set-up PCLK and pixel mode
enable output interface
0
1
0
0
pre-divided clock
HS_PLL (iif_dvi_on = 0) or
HS_DVI (iif_dvi_on = 1)
blank_
mode
X
X
1
0
ACTION
blank
Power-down
disable
normal
FUNCTION
MODE
all colours replaced by blank colour values
all registers set to default, like soft reset; all outputs LOW
all outputs reset but incoming data queued to trash
normal operation
83
7.17.10 P
For all data and control signals of the output interface
(PA[7:0], PB[7:0], PC[7:0], PD[7:0], PE[7:0], PF[7:0],
CSG[4:0], OUTEN and PWM) a programmable output
drive strength up to 15 mA is provided (in 8 steps and
starting at 2.9 mA); see Table 59.
For the PCLK output, a programmable output drive up to
30 mA is provided (in 8 steps and starting at 5.8 mA);
see Table 59.
Individual drive strength programming is possible for each
8-bit group of data signals (see Table 60). The drive
strength of control and clock signals are programmable
individually.
Table 59 Programmable drive strength
DS2
0
0
0
0
1
1
1
1
ROGRAMMABLE OUTPUT DRIVE STRENGTH
DS1
0
0
1
1
0
0
1
1
ACTION
DS0
0
1
0
1
0
1
0
1
DATA AND
CONTROL
OUTPUTS
(mA)
2.9
3.4
11
15
4
5
6
8
Product specification
SAA6703H
OUTPUT
PCLK
(mA)
5.8
6.8
10
12
16
22
30
8