saa6703h NXP Semiconductors, saa6703h Datasheet - Page 84

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saa6703h

Manufacturer Part Number
saa6703h
Description
Xga Dual Input Flat Panel Controller.
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
Table 60 Output interface drive strength
7.17.11 A
Every output pin, except pin PWM, can be delayed. The delay increment is 0.36 ns. The programming value is 5-bit wide
(see Table 61).
Table 61 Data to output mapping
2004 Apr 01
pin_drv_pa[2:0]
pin_drv_pb[2:0]
pin_drv_pc[2:0]
pin_drv_pd[2:0]
pin_drv_pe[2:0]
pin_drv_pf[2:0]
pin_drv_csg0[2:0]
pin_drv_csg1[2:0]
pin_drv_csg2[2:0]
pin_drv_csg3[2:0]
pin_drv_csg4[2:0]
pin_drv_pwm[2:0]
pin_drv_outen[2:0]
pin_drv_pclk[2:0]
OI_PAD
OI_PBD
OI_PCD
OI_PDD
OI_PED
OI_PFD
OI_CTRL1
OI_G0BD
OI_G1BD
OI_G2D
OI_G3D
OI_G4D
XGA dual input flat panel controller
BIT
DJUSTABLE OUTPUT DELAYS
REGISTER
output drive strength for PA
output drive strength for PB
output drive strength for PC
output drive strength for PD
output drive strength for PE
output drive strength for PF
output drive strength for CSG0
output drive strength for CSG1
output drive strength for CSG2
output drive strength for CSG3
output drive strength for CSG4
output drive strength for PWM
output drive strength for OUTEN
output drive strength for PCLK
DESCRIPTION
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
PCLK_pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
BIT
84
from 2.9 mA (reset) to 15 mA; see Table 59
from 5.8 mA (reset) to 30 mA; see Table 59
PA
PB
PC
PD
PE
PF
PCLK
CSG0
CSG1
CSG2
CSG3
CSG4
REMARK
OUTPUT
Product specification
SAA6703H

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