pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 177

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

HA1..0
Note: If RAH1, RAH2 contain the identical value, the combination 00 will be omitted.
C/R
LA
Note: The receive status byte is duplicated into the RFIFO (clock mode 0-2) following
Semiconductor Group
HA1..0 is significant only in 2-byte address modes.
the last byte of the corresponding frame. In clock mode 3 a modified receive status
byte is copied into RFIFO containing IOM-port and channel address of the
received frame. Please refer to chapter 2.2.7.6 the RFIFO in clock mode 3.
High byte Address compare.
In operating modes which provide high byte address recognition, the SACCO
compares the high byte of a 2-byte address with the contents of two
individual programmable registers (RAH1, RAH2) and the fixed values FEH
and FCH (group address). Depending on the result of the comparison, the
following bit combinations are possible:
10…RAH1 has been recognized.
00…RAH2 has been recognized.
01…group address has been recognized.
Command/Response; significant only, if 2-byte address mode has been
selected. Value of the C/R bit (bit of high address byte) in the received frame.
Low byte Address compare.
The low byte address of a 2-byte address field or the single address byte of
a 1-byte address field is compared with two programmable registers (RAL1,
RAL2). Depending on the result of the comparison LA is set.
0…RAL2 has been recognized,
1…RAL1 has been recognized.
In non-auto mode, according to the X.25 LAP B-protocol, RAL1/RAL2 may
be programmed to differ between COMMAND/RESPONSE frames.
177
Detailed Register Description
PEB 20550
PEF 20550
01.96