pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 49

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

INTEST supports internal chip testing.
When the TAP-controller is in the state "update DR", all inputs are updated internally with
the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Note: 001 (INTEST) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to preload (TDI)/shift out (TDO) the boundary scan with a test vector. Both activities
are transparent to the system functionality.
IDCODE, the 32-bit identification register is serially read out via TDO. It contains the
version number (4 bit), the device code (16 bit) and the manufacturer code (11 bits). The
LSB is fixed to "1".
Note: In the state "test logic reset" the code "011" is loaded into the instruction code
BYPASS, a bit entering TDI is shifted to TDO after one TCK-clock cycle.
2.2.6
The EPIC-1 is fully compatible to the Siemens PEB 2055 (EPIC-1, Version A3). It
includes the following functional enhancements:
– Direct access to all registers also in demultiplexed mode
– PCM-mode 3
– Software activation of external reset
– Error correction
– Additional clock shift features PCM (register PCSR)
For detailed information refer to appendix 9.1.
2.2.6.1 PCM-Interface
The PCM-interface formats the data transmitted or received at the PCM-highways. It can
be configured as one (max. 8192 kbit/s), two (max. 4096 kbit/s) or four (max. 2048 kbit/
s) PCM-ports, consisting each of a data receive (RxD#), a data transmit (TxD#) and an
output tristate indication line (TSC#).
Port configuration, data rates, clock shift and sampling conditions are programmable.
The newly implemented PCM-mode 3 is similar to mode 1 (two PCM-highways). Unlike
mode 1 the pins TxD1, TxD3 are not tristated but drive the inverted values of TxD0,
TxD2.
Semiconductor Group
TDI
register
EPIC
®
0001
0010
-1
0000 0000 0001 0011
0000 0000 0001 0011
49
0000 1000 001
0000 1000 001
Functional Description
1
1
PEB 20550
PEF 20550
for V1.3
TDO
01.96