pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 337

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

synchronization status (gained or lost) can be read from the STAR_E register (PSS bit)
and each status change generates an interrupt (ISTA_E:PFI).
It should be noted that the framing supervision function is optional, i.e. it is also allowed
to apply a PFS signal having a period of several frame periods e.g. 4 kHz, 2 kHz, … .
The STAR_E:PSS bit will then be at logical 0 all the time, which does however not affect
the proper operation of the ELIC.
The following register bits are used in conjunction with the PCM framing supervision:
Interrupt Status Register EPIC
ISTA_E:
The ISTA_E register should be read after an interrupt in order to determine the interrupt
source. In connection with the PCM framing control one maskable (MASK_E) interrupt
bit is provided by the ELIC:
PFI:
Status Register EPIC
STAR_E:
The STAR_E register bits do not generate interrupts and are not modified by reading
STAR_E. However, each change of the PSS bit (0
ISTA_E:PFI interrupt.
PSS:
Semiconductor Group
bit 7
bit 7
MAC
TIN
PCM Framing Interrupt; if this bit is set to logical 1, the STAR_E:PSS
bit has changed its polarity. To determine whether the PCM interface
is synchronized or not, STAR_E must be read. The PFI bit is reset by
reading ISTA_E.
PCM
synchronized, the PSS bit is set to logical 1. The PSS bit is reset to
logical 0 if there is a mismatch between the PBNR value and the
applied clock and framing signals (PDC/PFS) or if OMDR:OMS0 = 0.
TAC
SFI
®
Synchronization
MFFI
PSS
®
MFTO
MAC
337
read/write reset value:
read
Status;
MFAB
PFI
while
reset value:
MFAE
1 and 1
PIM
the PCM
Application Hints
MFRW
SIN
0) causes an
00
05
PEB 20550
interface
PEF 20550
H
H
bit 0
bit 0
MFFE
SOV
01.96
is