pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 233

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

Examples
1) In CFI mode 0, with a frame consisting of 32 timeslots, the following timing
Figure 80
Timing Signals for CFI Bit Shift Example 1
The framing signal source PFS shall mark CFI timeslot 31, bit 1 in downstream direction
and CFI timeslot 0, bit 5 in upstream direction. The data shall be transmitted and
sampled with the falling CRCL edge. The timing of the FSC and DCL output signals shall
be as shown in figure 80. The PFS signal is sampled with the rising PDC edge.
The following CFI register values result:
Since PFS marks the downstream bit 1, the CBSR:CDS bits must be set to ‘000’,
according to table 34.
If the CBSR:CDS bits are set to ‘000’, PFS marks the timeslot TSN – 1, according to
table 34.
PFS shall mark CFI timeslot 31, i.e. TSN – 1 = 31, or
TSN = 31 + 1 = (32)
From this it follows that:
CTAR:TSN6 … 0 = TSN + 2 = 0 + 2 = 2
The upstream CFI frame shall be shifted by 4 bits to the left (TS31, bit 1 + 4 bits yields
in TS0, bit 5).
Semiconductor Group
PFS
PDC/
CRCL
DD#
DU#
FSC
DCL
relationship between the framing signal source PFS and the data signals is required:
TS31, Bit 2
TS0,
0
Bit 6
mod 32
1
TS31, Bit 1
TS0, Bit 5
= 0
TS31, Bit 0
TS0,
Bit 4
D
= 0000010
233
TS0,
TS0,
Bit 7
Bit 3
B
; i.e. CTAR = 02
TS0,
TS0,
Bit 6
Bit 2
Application Hints
Condition:
CMD1
PMOD PSM = 1
CFI Mode 0
CMD2 CXF = 1
CMD2
CMD2
CMD2 COC = 0
H
:
PEB 20550
:
:
:
:
:
PEF 20550
CSM
CRR
FC2
...0
=
=
1
0
ITT08059
=
01.96
011