pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 325

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

PEB 20550
PEF 20550
Application Hints
If the CFI is selected as source/destination of the synchronous transfer, the contents of
the data register STDA (STDB) are exchanged with the control memory data field. It is
therefore necessary to initialize the corresponding control memory code field as
‘ P channel’ (code ‘1001’). Also refer to chapter 5.6.
Since the P channel set-up at the CFI only allows a channel bandwidth of 64 kBit/s, the
synchronous transfer utility also allows only 64 kBit/s channels at the CFI.
The ELIC generates interrupts guiding through the synchronous transfer. Upon the
ISTA_E:SIN interrupt the data registers STDA (STDB) may be accessed for some time.
If the data register of an active channel has not been accessed at the end of this time
interval the ISTA:SOV interrupt is generated, before the ELIC performs the transfer to
the selected memory locations. If the P fails to overwrite the data register with a new
value, the value previously received from the timeslot pointed to by SARA (SARB) will
be transmitted. The ISTA_E:SIN and SOV interrupts are generated periodically at fixed
time points within the frame regardless of the actual positions of the involved timeslots.
The repetition cycle of the synchronous transfer is identical to a frame length (125 s).
The access window is closed for at most, 16 RCL periods per active channel + 1 RCL
period, leaving a very long access time.
This behavior is also shown in figure 112:
Frame n
Frame n + 1
max. 17 (33) RCL Periods
125 µs
STCR : TAE(TBE) = 1
SIN
(SOV) SIN
(SOV)
SIN
µP Access Window Open
P µ
Access Window Open
ITD08092
Figure 112
Synchronous Transfer Flow Diagram
Example
In a typical IOM-2 application, the RCL frequency is 4096 kHz, i.e. an RCL period lasts
244 ns. The IOM-2 frame duration is 125 s. If one synchronous channel is enabled, the
access window is open for 121 s and closed for 4 s. If both synchronous channels are
enabled, the access window is open for 117 s and closed for 8 s.
Semiconductor Group
325
01.96