pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 7
![no-image](/images/no-image-200.jpg)
pef20550
Manufacturer Part Number
pef20550
Description
Extended Line Card Interface Controller Elic
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF20550.pdf
(407 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
pef20550H
Manufacturer:
FAI
Quantity:
543
- Current page: 7 of 407
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Table of Contents
4.6.28
4.6.29
4.6.30
4.6.31
4.6.32
4.6.33
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.7.8
4.7.9
4.7.10
4.7.11
4.7.12
4.7.13
4.7.14
4.7.15
4.7.16
4.7.17
4.7.18
4.7.19
4.7.20
4.7.21
4.7.22
4.7.23
4.7.24
4.7.25
4.7.26
4.7.27
4.7.28
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
Semiconductor Group
Status Register EPIC®-1 (STAR_E) . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Command Register EPIC®-1 (CMDR_E) . . . . . . . . . . . . . . . . . . . . . . . .156
Interrupt Status Register EPIC®-1 (ISTA_E) . . . . . . . . . . . . . . . . . . . . . .158
Mask Register EPIC
Operation Mode Register (OMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Version Number Status Register (VNSR) . . . . . . . . . . . . . . . . . . . . . . . .162
SACCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Receive FIFO (RFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Transmit FIFO (XFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Interrupt Status Register (ISTA_A/B) . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Mask Register (MASK_A/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Extended Interrupt Register (EXIR_A/B) . . . . . . . . . . . . . . . . . . . . . . . . .166
Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Mode Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Channel Configuration Register 1 (CCR1) . . . . . . . . . . . . . . . . . . . . . . .171
Channel Configuration Register 2 (CCR2) . . . . . . . . . . . . . . . . . . . . . . .173
Receive Length Check Register (RLCR) . . . . . . . . . . . . . . . . . . . . . . . . .174
Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Receive Status Register (RSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Receive HDLC-Control Register (RHCR) . . . . . . . . . . . . . . . . . . . . . . . .178
Transmit Address Byte 1 (XAD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Transmit Address Byte 2 (XAD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Receive Address Byte Low Register 1 (RAL1) . . . . . . . . . . . . . . . . . . . .179
Receive Address Byte Low Register 2 (RAL2) . . . . . . . . . . . . . . . . . . . .180
Receive Address Byte High Register 1 (RAH1) . . . . . . . . . . . . . . . . . . .180
Receive Address Byte High Register 2 (RAH2) . . . . . . . . . . . . . . . . . . .181
Receive Byte Count Low (RBCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Receive Byte Count High (RBCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Transmit Byte Count Low (XBCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Transmit Byte Count High (XBCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Time Slot Assignment Register Transmit (TSAX) . . . . . . . . . . . . . . . . . .183
Time Slot Assignment Register Receive (TSAR) . . . . . . . . . . . . . . . . . .184
Transmit Channel Capacity Register (XCCR) . . . . . . . . . . . . . . . . . . . . .184
Receive Channel Capacity Register (RCCR) . . . . . . . . . . . . . . . . . . . . .185
Version Status Register (VSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
Arbiter Mode Register (AMO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
Arbiter State Register (ASTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Suspend Counter Value Register (SCV) . . . . . . . . . . . . . . . . . . . . . . . . .187
D-Channel Enable Register IOM-Port 0 (DCE0) . . . . . . . . . . . . . . . . . . .188
D-Channel Enable Register IOM-Port 1 (DCE1) . . . . . . . . . . . . . . . . . . .188
D-Channel Enable Register IOM-Port 2 (DCE2) . . . . . . . . . . . . . . . . . . .188
®
-1 (MASK_E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
7
PEB 20550
Page
01.96
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