pef82902 Infineon Technologies Corporation, pef82902 Datasheet - Page 109

• Manufacturer Part Number: pef82902
• Description: 4b3t Second Generation Modular Isdn Nt Intelligent Extended
• Manufacturer: Infineon Technologies Corporation

2.6
The T-SMINT
of the D- channel protocol (LAPD) or B-channel protocols. By setting the enable HDLC
channel bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register the HDLC controller can
access the D or B-channels or any combination of them e.g. 18 bit IDSL data (2B+D).
The HDLC transceiver in the T-SMINT
based communication: flag generation/recognition, bit stuffing, CRC check and address
recognition.
The HDLC controller contains a 64 byte FIFO in both receive and transmit direction
which is implemented as a cyclic buffer. The transceivers read and write data
sequentially with constant data rate, whereas the data transfer between FIFO and C
interface uses a block oriented protocol with variable block sizes.
2.6.1
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus, the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a LAPD two-byte address is shown below.
•
For the address recognition the T-SMINT
individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the
“group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which is set to ’1’ according to the LAPD protocol.
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODEH register:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
All frames with valid addresses are accepted and the bytes following the address are
transferred to the P via RFIFO. Additional information is available in RSTA.
Transparent mode 0 (MDS2-0 = ’110’).
Data Sheet
SAPI1, 2, SAPG
High Address Byte
HDLC Controller
Message Transfer Modes
â
IX contains a HDLC controller which can be used for the layer-2 functions
two-byte (MDS = ’011’) address comparison
Full address recognition with one-byte (MDS = ’010’) or
C/R 0
â
IX performs the framing functions used in HDLC
â
95
IX contains four programmable registers for
TEI 1, 2, TEIG
Low Address Byte
Functional Description
EA
PEF 81902
2001-11-12